diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2018-02-28 06:09:57 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-06 00:18:20 -0500 |
commit | 26b91946031a88293c7ce563ff923802af6509ce (patch) | |
tree | 9b7ad56e7feb381b903f0c07a988114cdec0302f /drivers/gpu/nvgpu/gv11b | |
parent | 848af2ce6de6140323a6ffe3075bf8021e119434 (diff) |
gpu: nvgpu: gv11b: Correct PMU PG enabled masks.
PMU ucode records supported feature list for a
particular chip as support mask sent
via PMU_PG_PARAM_CMD_GR_INIT_PARAM.
It then enables selective feature list through
enable mask sent via
PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd.
Right now only ELPG state machine mask was enabled.
Only ELPG state machine was getting executed
but other crucial steps in ELPG entry/exit sequence
were getting skipped.
Bug 200392620.
Bug 200296076.
Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665767
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 7dd4f8f4..32e751d9 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -446,7 +446,7 @@ int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
446 | cmd.cmd.pg.gr_init_param_v1.sub_cmd_id = | 446 | cmd.cmd.pg.gr_init_param_v1.sub_cmd_id = |
447 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | 447 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; |
448 | cmd.cmd.pg.gr_init_param_v1.featuremask = | 448 | cmd.cmd.pg.gr_init_param_v1.featuremask = |
449 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; | 449 | NVGPU_PMU_GR_FEATURE_MASK_ALL; |
450 | 450 | ||
451 | gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); | 451 | gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); |
452 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 452 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
@@ -476,7 +476,15 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) | |||
476 | cmd.cmd.pg.sf_mask_update.ctrl_id = | 476 | cmd.cmd.pg.sf_mask_update.ctrl_id = |
477 | PMU_PG_ELPG_ENGINE_ID_GRAPHICS; | 477 | PMU_PG_ELPG_ENGINE_ID_GRAPHICS; |
478 | cmd.cmd.pg.sf_mask_update.enabled_mask = | 478 | cmd.cmd.pg.sf_mask_update.enabled_mask = |
479 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; | 479 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING | |
480 | NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING | | ||
481 | NVGPU_PMU_GR_FEATURE_MASK_UNBIND | | ||
482 | NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE | | ||
483 | NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY | | ||
484 | NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE | | ||
485 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM | | ||
486 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC | | ||
487 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG; | ||
480 | 488 | ||
481 | gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); | 489 | gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); |
482 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 490 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |