From 26b91946031a88293c7ce563ff923802af6509ce Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 28 Feb 2018 16:39:57 +0530 Subject: gpu: nvgpu: gv11b: Correct PMU PG enabled masks. PMU ucode records supported feature list for a particular chip as support mask sent via PMU_PG_PARAM_CMD_GR_INIT_PARAM. It then enables selective feature list through enable mask sent via PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd. Right now only ELPG state machine mask was enabled. Only ELPG state machine was getting executed but other crucial steps in ELPG entry/exit sequence were getting skipped. Bug 200392620. Bug 200296076. Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1665767 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 7dd4f8f4..32e751d9 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -446,7 +446,7 @@ int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) cmd.cmd.pg.gr_init_param_v1.sub_cmd_id = PMU_PG_PARAM_CMD_GR_INIT_PARAM; cmd.cmd.pg.gr_init_param_v1.featuremask = - PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; + NVGPU_PMU_GR_FEATURE_MASK_ALL; gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, @@ -476,7 +476,15 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) cmd.cmd.pg.sf_mask_update.ctrl_id = PMU_PG_ELPG_ENGINE_ID_GRAPHICS; cmd.cmd.pg.sf_mask_update.enabled_mask = - PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; + NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING | + NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING | + NVGPU_PMU_GR_FEATURE_MASK_UNBIND | + NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE | + NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY | + NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE | + NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM | + NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC | + NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG; gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, -- cgit v1.2.2