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authorSeema Khowala <seemaj@nvidia.com>2017-03-10 15:18:40 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-14 22:50:05 -0400
commitd5fe11091b6d74016e482d9c41580924cc70f520 (patch)
tree1b33618a5fc1ecf460630ff5aab6e6c0e5876fc4 /drivers/gpu/nvgpu/gv11b/mc_gv11b.c
parenta29521e8d84241ea27b83f14f80547a2da601a97 (diff)
gpu: nvgpu: gv11b: fix stall interrupt enablement
Currently priv, pbus and ltc interrupts are enabled as non-stall but being handled in stall isr. Fix is to configure them as stall interrupt. Change-Id: I86adc04f480d5f4befe7e9255b582ce13fa4efc1 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1319018 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/mc_gv11b.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index 65aad786..83c03029 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -30,8 +30,11 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
30 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 30 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
31 0xffffffff); 31 0xffffffff);
32 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = 32 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
33 mc_intr_pfifo_pending_f() 33 mc_intr_pfifo_pending_f() |
34 | eng_intr_mask; 34 mc_intr_priv_ring_pending_f() |
35 mc_intr_pbus_pending_f() |
36 mc_intr_ltc_pending_f() |
37 eng_intr_mask;
35 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), 38 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
36 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); 39 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
37 40
@@ -39,9 +42,6 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
39 0xffffffff); 42 0xffffffff);
40 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = 43 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
41 mc_intr_pfifo_pending_f() 44 mc_intr_pfifo_pending_f()
42 | mc_intr_priv_ring_pending_f()
43 | mc_intr_ltc_pending_f()
44 | mc_intr_pbus_pending_f()
45 | eng_intr_mask; 45 | eng_intr_mask;
46 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), 46 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
47 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); 47 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);