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authorseshendra Gadagottu <sgadagottu@nvidia.com>2016-09-13 16:08:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-09-21 18:14:00 -0400
commit8fdf40a849f19dc2f00aacce976ed2e22dbb08f4 (patch)
treea01d2ecfc53f292890ab49ee0c26acedb85a1686 /drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
parentf1f9e2a3e6957470f479de6de7802c32c78888bd (diff)
gpu: gv11b: create modified runlist
Create gv11b runlist for channel and tsg in the new specified way. Also set runlist entry size for gv11b. Bug 1735760 Change-Id: Ifd421cd71180e9d02303f4cfc92a59fd74d6d893 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1220258 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h46
1 files changed, 23 insertions, 23 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
index c6f51acb..9cd2096a 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
@@ -462,7 +462,7 @@ static inline u32 ram_rl_entry_chan_inst_target_f(u32 v)
462{ 462{
463 return (v & 0x3) << 4; 463 return (v & 0x3) << 4;
464} 464}
465static inline u32 ram_rl_entry_chan_inst_target_target_sys_mem_ncoh_v(void) 465static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void)
466{ 466{
467 return 0x00000003; 467 return 0x00000003;
468} 468}
@@ -470,19 +470,19 @@ static inline u32 ram_rl_entry_chan_userd_target_f(u32 v)
470{ 470{
471 return (v & 0x3) << 6; 471 return (v & 0x3) << 6;
472} 472}
473static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_v(void) 473static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void)
474{ 474{
475 return 0x00000000; 475 return 0x00000000;
476} 476}
477static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_nvlink_coh_v(void) 477static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void)
478{ 478{
479 return 0x00000001; 479 return 0x00000001;
480} 480}
481static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_coh_v(void) 481static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void)
482{ 482{
483 return 0x00000002; 483 return 0x00000002;
484} 484}
485static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_ncoh_v(void) 485static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void)
486{ 486{
487 return 0x00000003; 487 return 0x00000003;
488} 488}
@@ -494,18 +494,6 @@ static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v)
494{ 494{
495 return (v & 0xffffffff) << 0; 495 return (v & 0xffffffff) << 0;
496} 496}
497static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_inst_ptr_align_shift_v(void)
498{
499 return 0x0000000c;
500}
501static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_ptr_align_shift_v(void)
502{
503 return 0x00000008;
504}
505static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_align_shift_v(void)
506{
507 return 0x00000008;
508}
509static inline u32 ram_rl_entry_chid_f(u32 v) 497static inline u32 ram_rl_entry_chid_f(u32 v)
510{ 498{
511 return (v & 0xfff) << 0; 499 return (v & 0xfff) << 0;
@@ -526,7 +514,7 @@ static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v)
526{ 514{
527 return (v & 0xf) << 16; 515 return (v & 0xf) << 16;
528} 516}
529static inline u32 ram_rl_entry_tsg_timeslice_scale_entry_tsg_timeslice_scale_3_v(void) 517static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void)
530{ 518{
531 return 0x00000003; 519 return 0x00000003;
532} 520}
@@ -534,11 +522,11 @@ static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v)
534{ 522{
535 return (v & 0xff) << 24; 523 return (v & 0xff) << 24;
536} 524}
537static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_128_v(void) 525static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void)
538{ 526{
539 return 0x00000080; 527 return 0x00000080;
540} 528}
541static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_disable_v(void) 529static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void)
542{ 530{
543 return 0x00000000; 531 return 0x00000000;
544} 532}
@@ -546,15 +534,15 @@ static inline u32 ram_rl_entry_tsg_length_f(u32 v)
546{ 534{
547 return (v & 0xff) << 0; 535 return (v & 0xff) << 0;
548} 536}
549static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_init_v(void) 537static inline u32 ram_rl_entry_tsg_length_init_v(void)
550{ 538{
551 return 0x00000000; 539 return 0x00000000;
552} 540}
553static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_min_v(void) 541static inline u32 ram_rl_entry_tsg_length_min_v(void)
554{ 542{
555 return 0x00000001; 543 return 0x00000001;
556} 544}
557static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_max_v(void) 545static inline u32 ram_rl_entry_tsg_length_max_v(void)
558{ 546{
559 return 0x00000080; 547 return 0x00000080;
560} 548}
@@ -562,4 +550,16 @@ static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
562{ 550{
563 return (v & 0xfff) << 0; 551 return (v & 0xfff) << 0;
564} 552}
553static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void)
554{
555 return 0x0000000c;
556}
557static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void)
558{
559 return 0x00000008;
560}
561static inline u32 ram_rl_entry_chan_userd_align_shift_v(void)
562{
563 return 0x00000008;
564}
565#endif 565#endif