diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-06 08:56:34 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-04-10 14:23:03 -0400 |
commit | 4314771142e0b68810b8fa86ec45b6f6b4e24651 (patch) | |
tree | 32c1916385ecdb63073400e07e85266df5f8d412 /drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h | |
parent | e1200259ba3ad4ae416990b2f2abccb94565430f (diff) |
gpu: nvgpu: add broadcast address decode support for volta
With Volta we have more number of broadcast registers than previous chips
and we don't decode them right now in gr_gk20a_decode_priv_addr()
Add a new GR HAL decode_priv_addr() and set gr_gk20a_decode_priv_addr() for all
previous chips
Add and use gr_gv11b_decode_priv_addr() for Volta
gr_gv11b_decode_priv_addr() will decode all the broadcast registers and set
the broadcast flags apporiately
Define below new broadcast types
PRI_BROADCAST_FLAGS_PMMGPC
PRI_BROADCAST_FLAGS_PMM_GPCS
PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA
PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB
PRI_BROADCAST_FLAGS_PMMFBP
PRI_BROADCAST_FLAGS_PMM_FBPS
PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC
PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP
Bug 200398811
Jira NVGPU-556
Change-Id: Ic673b357a75b6af3d24a4c16bb5b6bc15974d5b7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1690026
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h new file mode 100644 index 00000000..c71f4c9c --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * GV11B/GV100 Graphics Context Pri Register Addressing | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef GR_PRI_GV11B_H | ||
25 | #define GR_PRI_GV11B_H | ||
26 | |||
27 | /* | ||
28 | * These convenience macros are generally for use in the management/modificaiton | ||
29 | * of the context state store for gr/compute contexts. | ||
30 | */ | ||
31 | |||
32 | /* Broadcast PMM defines */ | ||
33 | #define NV_PERF_PMMFBP_FBPGS_LTC 0x00250800 | ||
34 | #define NV_PERF_PMMFBP_FBPGS_ROP 0x00250A00 | ||
35 | #define NV_PERF_PMMGPC_GPCGS_GPCTPCA 0x00250000 | ||
36 | #define NV_PERF_PMMGPC_GPCGS_GPCTPCB 0x00250200 | ||
37 | #define NV_PERF_PMMGPC_GPCS 0x00278000 | ||
38 | #define NV_PERF_PMMFBP_FBPS 0x0027C000 | ||
39 | |||
40 | #define PRI_PMMGS_ADDR_WIDTH 9 | ||
41 | #define PRI_PMMS_ADDR_WIDTH 14 | ||
42 | |||
43 | /* Get the offset to be added to the chiplet base addr to get the unicast address */ | ||
44 | #define PRI_PMMGS_OFFSET_MASK(addr) ((addr) & ((1 << PRI_PMMGS_ADDR_WIDTH) - 1)) | ||
45 | #define PRI_PMMGS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMGS_ADDR_WIDTH) - 1))) | ||
46 | |||
47 | #define PRI_PMMS_ADDR_MASK(addr) ((addr) & ((1 << PRI_PMMS_ADDR_WIDTH) - 1)) | ||
48 | #define PRI_PMMS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMS_ADDR_WIDTH) - 1))) | ||
49 | |||
50 | #endif /* GR_PRI_GV11B_H */ | ||