gpu: nvgpu: use chip specific zbc_c/z format reg

Use chip specific gpcs_swdx_dss_zbc_c_format_reg
and gpcs_swdx_dss_zbc_z_format_reg. These registers
are different for gv11b/gv100 from gp10b/gp106.

Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 17e5e9e3..b69e69bd 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -102,6 +102,8 @@ int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
 int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc,
                                                         u32 gpc_exception);
 void gr_gv11b_enable_gpc_exceptions(struct gk20a *g);
+u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g);
+u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g);
 int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 bool *post_event);
 int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr,