From e9de95d7e0629c40b5ceb56c07de319bedd3339f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 9 Jan 2018 14:33:51 -0800 Subject: gpu: nvgpu: use chip specific zbc_c/z format reg Use chip specific gpcs_swdx_dss_zbc_c_format_reg and gpcs_swdx_dss_zbc_z_format_reg. These registers are different for gv11b/gv100 from gp10b/gp106. Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1635091 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 17e5e9e3..b69e69bd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -102,6 +102,8 @@ int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, u32 gpc_exception); void gr_gv11b_enable_gpc_exceptions(struct gk20a *g); +u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g); +u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g); int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event); int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, -- cgit v1.2.2