gpu: nvgpu: gv11b: add a function to reset pbdma and eng faulted

When Host receives a page fault signal from a CE, Host will immediately
set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel
and will trigger a preempt of the TSG/channel.
A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0
and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel.
If a TSG has a faulted channel, Host will not schedule the entire TSG
agin until all _FAULTED bits from channels in the TSG are cleared by SW.
This function will be required for ce page fault handling.

JIRA GPUT19X-46
JIRA GPUT19X-12

Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1509776
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
index 94b7934f..03cca839 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
@@ -38,4 +38,7 @@
 
 struct gpu_ops;
 void gv11b_init_fifo(struct gpu_ops *gops);
+void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
+                        struct channel_gk20a *refch,
+                        u32 faulted_pbdma, u32 faulted_engine);
 #endif