From 5cda5a3074e4c7dae1857e1dfdf55017b0450786 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Jun 2017 22:10:49 -0700 Subject: gpu: nvgpu: gv11b: add a function to reset pbdma and eng faulted When Host receives a page fault signal from a CE, Host will immediately set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel and will trigger a preempt of the TSG/channel. A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0 and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel. If a TSG has a faulted channel, Host will not schedule the entire TSG agin until all _FAULTED bits from channels in the TSG are cleared by SW. This function will be required for ce page fault handling. JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1509776 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 94b7934f..03cca839 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -38,4 +38,7 @@ struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); +void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, + struct channel_gk20a *refch, + u32 faulted_pbdma, u32 faulted_engine); #endif -- cgit v1.2.2