diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-09-14 08:48:07 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-15 15:48:22 -0400 |
commit | f720b309f1ea87a301bcb216983396f3d9c55abc (patch) | |
tree | 7776523be5dadc1a1af918e1d3f4525beadba075 /drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |
parent | 52f50addc6cedf57fc3d8ff06314921499fb59e3 (diff) |
gpu: nvgpu: add tsg_verify_status_faulted operation
Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as
g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100
This API will check if channel has ENG_FAULTED status set, if yes it will clear
CE method buffer in case saved out channel is same as faulted channel
We need to write 0 to method count to invalidate CE method buffer
Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100
Bug 200327095
Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1d5e593c..b4e4b875 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1811,3 +1811,38 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, | |||
1811 | else | 1811 | else |
1812 | *pbdma_id = FIFO_INVAL_PBDMA_ID; | 1812 | *pbdma_id = FIFO_INVAL_PBDMA_ID; |
1813 | } | 1813 | } |
1814 | |||
1815 | static bool gk20a_fifo_channel_status_is_eng_faulted(struct gk20a *g, u32 chid) | ||
1816 | { | ||
1817 | u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); | ||
1818 | |||
1819 | return ccsr_channel_eng_faulted_v(channel) == | ||
1820 | ccsr_channel_eng_faulted_true_v(); | ||
1821 | } | ||
1822 | |||
1823 | void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch) | ||
1824 | { | ||
1825 | struct gk20a *g = ch->g; | ||
1826 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
1827 | |||
1828 | /* | ||
1829 | * If channel has FAULTED set, clear the CE method buffer | ||
1830 | * if saved out channel is same as faulted channel | ||
1831 | */ | ||
1832 | if (!gk20a_fifo_channel_status_is_eng_faulted(g, ch->chid)) | ||
1833 | return; | ||
1834 | |||
1835 | if (tsg->eng_method_buffers == NULL) | ||
1836 | return; | ||
1837 | |||
1838 | /* | ||
1839 | * CE method buffer format : | ||
1840 | * DWord0 = method count | ||
1841 | * DWord1 = channel id | ||
1842 | * | ||
1843 | * It is sufficient to write 0 to method count to invalidate | ||
1844 | */ | ||
1845 | if ((u32)ch->chid == | ||
1846 | nvgpu_mem_rd32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 1)) | ||
1847 | nvgpu_mem_wr32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 0, 0); | ||
1848 | } | ||