diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-11-16 02:21:19 -0500 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2017-11-16 02:21:35 -0500 |
commit | ba8dc318595f597308902ad16ffed89bdbe7000f (patch) | |
tree | e882886e0cbc05ac39473b95ead16ee50bd69c15 /drivers/gpu/nvgpu/gv100 | |
parent | 69e032653df5aae335764f6346703a1e55c96a2d (diff) | |
parent | 77a90d0b8d2eb1bbb207ae5f46b357f2d7cd07ab (diff) |
Merge remote-tracking branch 'remotes/origin/dev/linux-nvgpu-t19x' into linux-nvgpu
Bug 200363166
Change-Id: Ic662d7b44b673db28dc0aeba338ae67cf2a43d64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/bios_gv100.c | 108 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/bios_gv100.h | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fb_gv100.c | 184 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fb_gv100.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.c | 40 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.h | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 47 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | 34 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.c | 349 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.h | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gv100.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 769 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/mm_gv100.c | 55 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/mm_gv100.h | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/regops_gv100.c | 463 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/regops_gv100.h | 42 |
17 files changed, 2318 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.c b/drivers/gpu/nvgpu/gv100/bios_gv100.c new file mode 100644 index 00000000..9ca05a11 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.c | |||
@@ -0,0 +1,108 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/bios.h> | ||
24 | #include <nvgpu/nvgpu_common.h> | ||
25 | #include <nvgpu/timers.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | #include "gp106/bios_gp106.h" | ||
29 | #include "bios_gv100.h" | ||
30 | |||
31 | #include <nvgpu/hw/gv100/hw_pwr_gv100.h> | ||
32 | #include <nvgpu/hw/gv100/hw_bus_gv100.h> | ||
33 | |||
34 | #define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ | ||
35 | #define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ | ||
36 | |||
37 | #define SCRATCH_PREOS_PROGRESS 6 | ||
38 | #define PREOS_PROGRESS_MASK(r) ((r >> 12) & 0xf) | ||
39 | #define PREOS_PROGRESS_NOT_STARTED 0 | ||
40 | #define PREOS_PROGRESS_STARTED 1 | ||
41 | #define PREOS_PROGRESS_EXIT 2 | ||
42 | #define PREOS_PROGRESS_EXIT_SECUREMODE 3 | ||
43 | #define PREOS_PROGRESS_ABORTED 6 | ||
44 | |||
45 | #define SCRATCH_PMU_EXIT_AND_HALT 1 | ||
46 | #define PMU_EXIT_AND_HALT_SET(r, v) ((r & ~0x200UL) | v) | ||
47 | #define PMU_EXIT_AND_HALT_YES (0x1UL << 9) | ||
48 | |||
49 | #define SCRATCH_PRE_OS_RELOAD 1 | ||
50 | #define PRE_OS_RELOAD_SET(r, v) ((r & ~0x100UL) | v) | ||
51 | #define PRE_OS_RELOAD_YES (0x1UL << 8) | ||
52 | |||
53 | |||
54 | void gv100_bios_preos_reload_check(struct gk20a *g) | ||
55 | { | ||
56 | u32 progress = gk20a_readl(g, | ||
57 | bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); | ||
58 | |||
59 | if (PREOS_PROGRESS_MASK(progress) != PREOS_PROGRESS_NOT_STARTED) { | ||
60 | u32 reload = gk20a_readl(g, | ||
61 | bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD)); | ||
62 | |||
63 | gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD), | ||
64 | PRE_OS_RELOAD_SET(reload, PRE_OS_RELOAD_YES)); | ||
65 | } | ||
66 | } | ||
67 | |||
68 | int gv100_bios_preos_wait_for_halt(struct gk20a *g) | ||
69 | { | ||
70 | int err = -EINVAL; | ||
71 | u32 progress; | ||
72 | u32 tmp; | ||
73 | int preos_completed; | ||
74 | struct nvgpu_timeout timeout; | ||
75 | |||
76 | nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); | ||
77 | |||
78 | /* Check the progress */ | ||
79 | progress = gk20a_readl(g, bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); | ||
80 | |||
81 | if (PREOS_PROGRESS_MASK(progress) == PREOS_PROGRESS_STARTED) { | ||
82 | err = 0; | ||
83 | |||
84 | /* Complete the handshake */ | ||
85 | tmp = gk20a_readl(g, | ||
86 | bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT)); | ||
87 | |||
88 | gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT), | ||
89 | PMU_EXIT_AND_HALT_SET(tmp, PMU_EXIT_AND_HALT_YES)); | ||
90 | |||
91 | nvgpu_timeout_init(g, &timeout, | ||
92 | PMU_BOOT_TIMEOUT_MAX / | ||
93 | PMU_BOOT_TIMEOUT_DEFAULT, | ||
94 | NVGPU_TIMER_RETRY_TIMER); | ||
95 | |||
96 | do { | ||
97 | progress = gk20a_readl(g, | ||
98 | bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); | ||
99 | preos_completed = pwr_falcon_cpuctl_halt_intr_v( | ||
100 | gk20a_readl(g, pwr_falcon_cpuctl_r())) && | ||
101 | (PREOS_PROGRESS_MASK(progress) == | ||
102 | PREOS_PROGRESS_EXIT); | ||
103 | nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); | ||
104 | } while (!preos_completed && !nvgpu_timeout_expired(&timeout)); | ||
105 | } | ||
106 | |||
107 | return err; | ||
108 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.h b/drivers/gpu/nvgpu/gv100/bios_gv100.h new file mode 100644 index 00000000..c6433f57 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_BIOS_GV100_H | ||
24 | #define NVGPU_BIOS_GV100_H | ||
25 | |||
26 | struct gk20a; | ||
27 | |||
28 | void gv100_bios_preos_reload_check(struct gk20a *g); | ||
29 | int gv100_bios_preos_wait_for_halt(struct gk20a *g); | ||
30 | |||
31 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c new file mode 100644 index 00000000..0a2939bf --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c | |||
@@ -0,0 +1,184 @@ | |||
1 | /* | ||
2 | * GV100 FB | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | |||
27 | #include <nvgpu/dma.h> | ||
28 | #include <nvgpu/log.h> | ||
29 | #include <nvgpu/enabled.h> | ||
30 | #include <nvgpu/gmmu.h> | ||
31 | #include <nvgpu/nvgpu_common.h> | ||
32 | #include <nvgpu/kmem.h> | ||
33 | #include <nvgpu/nvgpu_mem.h> | ||
34 | #include <nvgpu/acr/nvgpu_acr.h> | ||
35 | #include <nvgpu/firmware.h> | ||
36 | #include <nvgpu/pmu.h> | ||
37 | #include <nvgpu/falcon.h> | ||
38 | |||
39 | #include "gk20a/gk20a.h" | ||
40 | #include "gv100/fb_gv100.h" | ||
41 | #include "gm20b/acr_gm20b.h" | ||
42 | |||
43 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> | ||
44 | #include <nvgpu/hw/gv100/hw_falcon_gv100.h> | ||
45 | #include <nvgpu/hw/gv100/hw_mc_gv100.h> | ||
46 | |||
47 | #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ | ||
48 | #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ | ||
49 | #define MEM_UNLOCK_TIMEOUT 3500 /* msec */ | ||
50 | |||
51 | void gv100_fb_reset(struct gk20a *g) | ||
52 | { | ||
53 | u32 val; | ||
54 | int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; | ||
55 | |||
56 | nvgpu_info(g, "reset gv100 fb"); | ||
57 | |||
58 | /* wait for memory to be accessible */ | ||
59 | do { | ||
60 | u32 w = gk20a_readl(g, fb_niso_scrub_status_r()); | ||
61 | if (fb_niso_scrub_status_flag_v(w)) { | ||
62 | nvgpu_info(g, "done"); | ||
63 | break; | ||
64 | } | ||
65 | nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT); | ||
66 | } while (--retries); | ||
67 | |||
68 | val = gk20a_readl(g, fb_mmu_priv_level_mask_r()); | ||
69 | val &= ~fb_mmu_priv_level_mask_write_violation_m(); | ||
70 | gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); | ||
71 | } | ||
72 | |||
73 | int gv100_fb_memory_unlock(struct gk20a *g) | ||
74 | { | ||
75 | struct nvgpu_firmware *mem_unlock_fw = NULL; | ||
76 | struct bin_hdr *hsbin_hdr = NULL; | ||
77 | struct acr_fw_header *fw_hdr = NULL; | ||
78 | u32 *mem_unlock_ucode = NULL; | ||
79 | u32 *mem_unlock_ucode_header = NULL; | ||
80 | u32 sec_imem_dest = 0; | ||
81 | u32 val = 0; | ||
82 | int err = 0; | ||
83 | |||
84 | nvgpu_log_fn(g, " "); | ||
85 | |||
86 | /* Check vpr enable status */ | ||
87 | val = gk20a_readl(g, fb_mmu_vpr_info_r()); | ||
88 | val &= ~fb_mmu_vpr_info_index_m(); | ||
89 | val |= fb_mmu_vpr_info_index_cya_lo_v(); | ||
90 | gk20a_writel(g, fb_mmu_vpr_info_r(), val); | ||
91 | val = gk20a_readl(g, fb_mmu_vpr_info_r()); | ||
92 | if (!(val & fb_mmu_vpr_info_cya_lo_in_use_m())) { | ||
93 | nvgpu_log_info(g, "mem unlock not required on this SKU, skipping"); | ||
94 | goto exit; | ||
95 | } | ||
96 | |||
97 | /* get mem unlock ucode binary */ | ||
98 | mem_unlock_fw = nvgpu_request_firmware(g, "mem_unlock.bin", 0); | ||
99 | if (!mem_unlock_fw) { | ||
100 | nvgpu_err(g, "mem unlock ucode get fail"); | ||
101 | err = -ENOENT; | ||
102 | goto exit; | ||
103 | } | ||
104 | |||
105 | /* Enable nvdec */ | ||
106 | g->ops.mc.enable(g, mc_enable_nvdec_enabled_f()); | ||
107 | |||
108 | /* nvdec falcon reset */ | ||
109 | nvgpu_flcn_reset(&g->nvdec_flcn); | ||
110 | |||
111 | hsbin_hdr = (struct bin_hdr *)mem_unlock_fw->data; | ||
112 | fw_hdr = (struct acr_fw_header *)(mem_unlock_fw->data + | ||
113 | hsbin_hdr->header_offset); | ||
114 | |||
115 | mem_unlock_ucode_header = (u32 *)(mem_unlock_fw->data + | ||
116 | fw_hdr->hdr_offset); | ||
117 | mem_unlock_ucode = (u32 *)(mem_unlock_fw->data + | ||
118 | hsbin_hdr->data_offset); | ||
119 | |||
120 | /* Patch Ucode singnatures */ | ||
121 | if (acr_ucode_patch_sig(g, mem_unlock_ucode, | ||
122 | (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset), | ||
123 | (u32 *)(mem_unlock_fw->data + fw_hdr->sig_dbg_offset), | ||
124 | (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc), | ||
125 | (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) { | ||
126 | nvgpu_err(g, "mem unlock patch signatures fail"); | ||
127 | err = -EPERM; | ||
128 | goto exit; | ||
129 | } | ||
130 | |||
131 | /* Clear interrupts */ | ||
132 | nvgpu_flcn_set_irq(&g->nvdec_flcn, false, 0x0, 0x0); | ||
133 | |||
134 | /* Copy Non Secure IMEM code */ | ||
135 | nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, 0, | ||
136 | (u8 *)&mem_unlock_ucode[ | ||
137 | mem_unlock_ucode_header[OS_CODE_OFFSET] >> 2], | ||
138 | mem_unlock_ucode_header[OS_CODE_SIZE], 0, false, | ||
139 | GET_IMEM_TAG(mem_unlock_ucode_header[OS_CODE_OFFSET])); | ||
140 | |||
141 | /* Put secure code after non-secure block */ | ||
142 | sec_imem_dest = GET_NEXT_BLOCK(mem_unlock_ucode_header[OS_CODE_SIZE]); | ||
143 | |||
144 | nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, sec_imem_dest, | ||
145 | (u8 *)&mem_unlock_ucode[ | ||
146 | mem_unlock_ucode_header[APP_0_CODE_OFFSET] >> 2], | ||
147 | mem_unlock_ucode_header[APP_0_CODE_SIZE], 0, true, | ||
148 | GET_IMEM_TAG(mem_unlock_ucode_header[APP_0_CODE_OFFSET])); | ||
149 | |||
150 | /* load DMEM: ensure that signatures are patched */ | ||
151 | nvgpu_flcn_copy_to_dmem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[ | ||
152 | mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2], | ||
153 | mem_unlock_ucode_header[OS_DATA_SIZE], 0); | ||
154 | |||
155 | nvgpu_log_info(g, "nvdec sctl reg %x\n", | ||
156 | gk20a_readl(g, g->nvdec_flcn.flcn_base + | ||
157 | falcon_falcon_sctl_r())); | ||
158 | |||
159 | /* set BOOTVEC to start of non-secure code */ | ||
160 | nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0); | ||
161 | |||
162 | /* wait for complete & halt */ | ||
163 | nvgpu_flcn_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT); | ||
164 | |||
165 | /* check mem unlock status */ | ||
166 | val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0); | ||
167 | if (val) { | ||
168 | nvgpu_err(g, "memory unlock failed, err %x", val); | ||
169 | err = -1; | ||
170 | goto exit; | ||
171 | } | ||
172 | |||
173 | nvgpu_log_info(g, "nvdec sctl reg %x\n", | ||
174 | gk20a_readl(g, g->nvdec_flcn.flcn_base + | ||
175 | falcon_falcon_sctl_r())); | ||
176 | |||
177 | exit: | ||
178 | if (mem_unlock_fw) | ||
179 | nvgpu_release_firmware(g, mem_unlock_fw); | ||
180 | |||
181 | nvgpu_log_fn(g, "done, status - %d", err); | ||
182 | |||
183 | return err; | ||
184 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h new file mode 100644 index 00000000..b6db262a --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * GV100 FB | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GV100_FB | ||
26 | #define _NVGPU_GV100_FB | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | void gv100_fb_reset(struct gk20a *g); | ||
31 | int gv100_fb_memory_unlock(struct gk20a *g); | ||
32 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c new file mode 100644 index 00000000..79862f6b --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * GV100 fifo | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "fifo_gv100.h" | ||
26 | |||
27 | #include <nvgpu/hw/gv100/hw_ccsr_gv100.h> | ||
28 | |||
29 | #define DEFAULT_FIFO_PREEMPT_TIMEOUT 0x3FFFFFUL | ||
30 | |||
31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g) | ||
32 | { | ||
33 | return ccsr_channel__size_1_v(); | ||
34 | } | ||
35 | |||
36 | u32 gv100_fifo_get_preempt_timeout(struct gk20a *g) | ||
37 | { | ||
38 | return DEFAULT_FIFO_PREEMPT_TIMEOUT; | ||
39 | } | ||
40 | |||
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h new file mode 100644 index 00000000..af6ad030 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * GV100 Fifo | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef FIFO_GV100_H | ||
26 | #define FIFO_GV100_H | ||
27 | |||
28 | #include <nvgpu/types.h> | ||
29 | struct gk20a; | ||
30 | |||
31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g); | ||
32 | u32 gv100_fifo_get_preempt_timeout(struct gk20a *g); | ||
33 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c new file mode 100644 index 00000000..8b50125e --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | |||
@@ -0,0 +1,47 @@ | |||
1 | /* | ||
2 | * GV100 Graphics Context | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "gr_ctx_gv100.h" | ||
27 | |||
28 | int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name) | ||
29 | { | ||
30 | u32 ver = g->params.gpu_arch + g->params.gpu_impl; | ||
31 | |||
32 | switch (ver) { | ||
33 | case NVGPU_GPUID_GV100: | ||
34 | sprintf(name, "%s/%s", "gv100", | ||
35 | GV100_NETLIST_IMAGE_FW_NAME); | ||
36 | break; | ||
37 | default: | ||
38 | nvgpu_err(g, "no support for GPUID %x", ver); | ||
39 | } | ||
40 | |||
41 | return 0; | ||
42 | } | ||
43 | |||
44 | bool gr_gv100_is_firmware_defined(void) | ||
45 | { | ||
46 | return true; | ||
47 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h new file mode 100644 index 00000000..2302d988 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef __GR_CTX_GV100_H__ | ||
23 | #define __GR_CTX_GV100_H__ | ||
24 | |||
25 | #include "gk20a/gr_ctx_gk20a.h" | ||
26 | #include "nvgpu_gpuid_t19x.h" | ||
27 | |||
28 | /* production netlist, one and only one from below */ | ||
29 | #define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D | ||
30 | |||
31 | int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name); | ||
32 | bool gr_gv100_is_firmware_defined(void); | ||
33 | |||
34 | #endif /*__GR_CTX_GV100_H__*/ | ||
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c new file mode 100644 index 00000000..430c7cd0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -0,0 +1,349 @@ | |||
1 | /* | ||
2 | * GV100 GPU GR | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/log.h> | ||
26 | #include <nvgpu/debug.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
29 | #include "gk20a/gk20a.h" | ||
30 | #include "gk20a/gr_gk20a.h" | ||
31 | |||
32 | #include "gv100/gr_gv100.h" | ||
33 | #include "gv11b/subctx_gv11b.h" | ||
34 | |||
35 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> | ||
36 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | ||
37 | |||
38 | /* | ||
39 | * Estimate performance if the given logical TPC in the given logical GPC were | ||
40 | * removed. | ||
41 | */ | ||
42 | static int gr_gv100_scg_estimate_perf(struct gk20a *g, | ||
43 | unsigned long *gpc_tpc_mask, | ||
44 | u32 disable_gpc_id, u32 disable_tpc_id, | ||
45 | int *perf) | ||
46 | { | ||
47 | struct gr_gk20a *gr = &g->gr; | ||
48 | int err = 0; | ||
49 | u32 scale_factor = 512UL; /* Use fx23.9 */ | ||
50 | u32 pix_scale = 1024*1024UL; /* Pix perf in [29:20] */ | ||
51 | u32 world_scale = 1024UL; /* World performance in [19:10] */ | ||
52 | u32 tpc_scale = 1; /* TPC balancing in [9:0] */ | ||
53 | u32 scg_num_pes = 0; | ||
54 | u32 min_scg_gpc_pix_perf = scale_factor; /* Init perf as maximum */ | ||
55 | u32 average_tpcs = 0; /* Average of # of TPCs per GPC */ | ||
56 | u32 deviation; /* absolute diff between TPC# and | ||
57 | * average_tpcs, averaged across GPCs | ||
58 | */ | ||
59 | u32 norm_tpc_deviation; /* deviation/max_tpc_per_gpc */ | ||
60 | u32 tpc_balance; | ||
61 | u32 scg_gpc_pix_perf; | ||
62 | u32 scg_world_perf; | ||
63 | u32 gpc_id; | ||
64 | u32 pes_id; | ||
65 | int diff; | ||
66 | bool is_tpc_removed_gpc = false; | ||
67 | bool is_tpc_removed_pes = false; | ||
68 | u32 max_tpc_gpc = 0; | ||
69 | u32 num_tpc_mask; | ||
70 | u32 *num_tpc_gpc = nvgpu_kzalloc(g, sizeof(u32) * | ||
71 | nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS)); | ||
72 | |||
73 | if (!num_tpc_gpc) | ||
74 | return -ENOMEM; | ||
75 | |||
76 | /* Calculate pix-perf-reduction-rate per GPC and find bottleneck TPC */ | ||
77 | for (gpc_id = 0; gpc_id < gr->gpc_count; gpc_id++) { | ||
78 | num_tpc_mask = gpc_tpc_mask[gpc_id]; | ||
79 | |||
80 | if ((gpc_id == disable_gpc_id) && num_tpc_mask & | ||
81 | (0x1 << disable_tpc_id)) { | ||
82 | /* Safety check if a TPC is removed twice */ | ||
83 | if (is_tpc_removed_gpc) { | ||
84 | err = -EINVAL; | ||
85 | goto free_resources; | ||
86 | } | ||
87 | /* Remove logical TPC from set */ | ||
88 | num_tpc_mask &= ~(0x1 << disable_tpc_id); | ||
89 | is_tpc_removed_gpc = true; | ||
90 | } | ||
91 | |||
92 | /* track balancing of tpcs across gpcs */ | ||
93 | num_tpc_gpc[gpc_id] = hweight32(num_tpc_mask); | ||
94 | average_tpcs += num_tpc_gpc[gpc_id]; | ||
95 | |||
96 | /* save the maximum numer of gpcs */ | ||
97 | max_tpc_gpc = num_tpc_gpc[gpc_id] > max_tpc_gpc ? | ||
98 | num_tpc_gpc[gpc_id] : max_tpc_gpc; | ||
99 | |||
100 | /* | ||
101 | * Calculate ratio between TPC count and post-FS and post-SCG | ||
102 | * | ||
103 | * ratio represents relative throughput of the GPC | ||
104 | */ | ||
105 | scg_gpc_pix_perf = scale_factor * num_tpc_gpc[gpc_id] / | ||
106 | gr->gpc_tpc_count[gpc_id]; | ||
107 | |||
108 | if (min_scg_gpc_pix_perf > scg_gpc_pix_perf) | ||
109 | min_scg_gpc_pix_perf = scg_gpc_pix_perf; | ||
110 | |||
111 | /* Calculate # of surviving PES */ | ||
112 | for (pes_id = 0; pes_id < gr->gpc_ppc_count[gpc_id]; pes_id++) { | ||
113 | /* Count the number of TPC on the set */ | ||
114 | num_tpc_mask = gr->pes_tpc_mask[pes_id][gpc_id] & | ||
115 | gpc_tpc_mask[gpc_id]; | ||
116 | |||
117 | if ((gpc_id == disable_gpc_id) && (num_tpc_mask & | ||
118 | (0x1 << disable_tpc_id))) { | ||
119 | |||
120 | if (is_tpc_removed_pes) { | ||
121 | err = -EINVAL; | ||
122 | goto free_resources; | ||
123 | } | ||
124 | num_tpc_mask &= ~(0x1 << disable_tpc_id); | ||
125 | is_tpc_removed_pes = true; | ||
126 | } | ||
127 | if (hweight32(num_tpc_mask)) | ||
128 | scg_num_pes++; | ||
129 | } | ||
130 | } | ||
131 | |||
132 | if (!is_tpc_removed_gpc || !is_tpc_removed_pes) { | ||
133 | err = -EINVAL; | ||
134 | goto free_resources; | ||
135 | } | ||
136 | |||
137 | if (max_tpc_gpc == 0) { | ||
138 | *perf = 0; | ||
139 | goto free_resources; | ||
140 | } | ||
141 | |||
142 | /* Now calculate perf */ | ||
143 | scg_world_perf = (scale_factor * scg_num_pes) / gr->ppc_count; | ||
144 | deviation = 0; | ||
145 | average_tpcs = scale_factor * average_tpcs / gr->gpc_count; | ||
146 | for (gpc_id =0; gpc_id < gr->gpc_count; gpc_id++) { | ||
147 | diff = average_tpcs - scale_factor * num_tpc_gpc[gpc_id]; | ||
148 | if (diff < 0) | ||
149 | diff = -diff; | ||
150 | deviation += diff; | ||
151 | } | ||
152 | |||
153 | deviation /= gr->gpc_count; | ||
154 | |||
155 | norm_tpc_deviation = deviation / max_tpc_gpc; | ||
156 | |||
157 | tpc_balance = scale_factor - norm_tpc_deviation; | ||
158 | |||
159 | if ((tpc_balance > scale_factor) || | ||
160 | (scg_world_perf > scale_factor) || | ||
161 | (min_scg_gpc_pix_perf > scale_factor) || | ||
162 | (norm_tpc_deviation > scale_factor)) { | ||
163 | err = -EINVAL; | ||
164 | goto free_resources; | ||
165 | } | ||
166 | |||
167 | *perf = (pix_scale * min_scg_gpc_pix_perf) + | ||
168 | (world_scale * scg_world_perf) + | ||
169 | (tpc_scale * tpc_balance); | ||
170 | free_resources: | ||
171 | nvgpu_kfree(g, num_tpc_gpc); | ||
172 | return err; | ||
173 | } | ||
174 | |||
175 | void gr_gv100_bundle_cb_defaults(struct gk20a *g) | ||
176 | { | ||
177 | struct gr_gk20a *gr = &g->gr; | ||
178 | |||
179 | gr->bundle_cb_default_size = | ||
180 | gr_scc_bundle_cb_size_div_256b__prod_v(); | ||
181 | gr->min_gpm_fifo_depth = | ||
182 | gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(); | ||
183 | gr->bundle_cb_token_limit = | ||
184 | gr_pd_ab_dist_cfg2_token_limit_init_v(); | ||
185 | } | ||
186 | |||
187 | void gr_gv100_cb_size_default(struct gk20a *g) | ||
188 | { | ||
189 | struct gr_gk20a *gr = &g->gr; | ||
190 | |||
191 | if (!gr->attrib_cb_default_size) | ||
192 | gr->attrib_cb_default_size = | ||
193 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); | ||
194 | gr->alpha_cb_default_size = | ||
195 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); | ||
196 | } | ||
197 | |||
198 | void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | ||
199 | { | ||
200 | } | ||
201 | |||
202 | void gr_gv100_init_sm_id_table(struct gk20a *g) | ||
203 | { | ||
204 | u32 gpc, tpc, sm, pes, gtpc; | ||
205 | u32 sm_id = 0; | ||
206 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); | ||
207 | u32 num_sm = sm_per_tpc * g->gr.tpc_count; | ||
208 | int perf, maxperf; | ||
209 | int err; | ||
210 | unsigned long *gpc_tpc_mask; | ||
211 | u32 *tpc_table, *gpc_table; | ||
212 | |||
213 | gpc_table = nvgpu_kzalloc(g, g->gr.tpc_count * sizeof(u32)); | ||
214 | tpc_table = nvgpu_kzalloc(g, g->gr.tpc_count * sizeof(u32)); | ||
215 | gpc_tpc_mask = nvgpu_kzalloc(g, sizeof(unsigned long) * | ||
216 | nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS)); | ||
217 | |||
218 | if (!gpc_table || !tpc_table || !gpc_tpc_mask) { | ||
219 | nvgpu_err(g, "Error allocating memory for sm tables"); | ||
220 | goto exit_build_table; | ||
221 | } | ||
222 | |||
223 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) | ||
224 | for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++) | ||
225 | gpc_tpc_mask[gpc] |= g->gr.pes_tpc_mask[pes][gpc]; | ||
226 | |||
227 | for (gtpc = 0; gtpc < g->gr.tpc_count; gtpc++) { | ||
228 | maxperf = -1; | ||
229 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { | ||
230 | for_each_set_bit(tpc, &gpc_tpc_mask[gpc], | ||
231 | g->gr.gpc_tpc_count[gpc]) { | ||
232 | perf = -1; | ||
233 | err = gr_gv100_scg_estimate_perf(g, | ||
234 | gpc_tpc_mask, gpc, tpc, &perf); | ||
235 | |||
236 | if (err) { | ||
237 | nvgpu_err(g, | ||
238 | "Error while estimating perf"); | ||
239 | goto exit_build_table; | ||
240 | } | ||
241 | |||
242 | if (perf >= maxperf) { | ||
243 | maxperf = perf; | ||
244 | gpc_table[gtpc] = gpc; | ||
245 | tpc_table[gtpc] = tpc; | ||
246 | } | ||
247 | } | ||
248 | } | ||
249 | gpc_tpc_mask[gpc_table[gtpc]] &= ~(0x1 << tpc_table[gtpc]); | ||
250 | } | ||
251 | |||
252 | for (tpc = 0, sm_id = 0; sm_id < num_sm; tpc++, sm_id += sm_per_tpc) { | ||
253 | for (sm = 0; sm < sm_per_tpc; sm++) { | ||
254 | u32 index = sm_id + sm; | ||
255 | |||
256 | g->gr.sm_to_cluster[index].gpc_index = gpc_table[tpc]; | ||
257 | g->gr.sm_to_cluster[index].tpc_index = tpc_table[tpc]; | ||
258 | g->gr.sm_to_cluster[index].sm_index = sm; | ||
259 | g->gr.sm_to_cluster[index].global_tpc_index = tpc; | ||
260 | nvgpu_log_info(g, | ||
261 | "gpc : %d tpc %d sm_index %d global_index: %d", | ||
262 | g->gr.sm_to_cluster[index].gpc_index, | ||
263 | g->gr.sm_to_cluster[index].tpc_index, | ||
264 | g->gr.sm_to_cluster[index].sm_index, | ||
265 | g->gr.sm_to_cluster[index].global_tpc_index); | ||
266 | |||
267 | } | ||
268 | } | ||
269 | |||
270 | g->gr.no_of_sm = num_sm; | ||
271 | nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); | ||
272 | exit_build_table: | ||
273 | nvgpu_kfree(g, gpc_table); | ||
274 | nvgpu_kfree(g, tpc_table); | ||
275 | nvgpu_kfree(g, gpc_tpc_mask); | ||
276 | } | ||
277 | |||
278 | void gr_gv100_load_tpc_mask(struct gk20a *g) | ||
279 | { | ||
280 | u64 pes_tpc_mask = 0x0ULL; | ||
281 | u32 gpc, pes; | ||
282 | u32 num_tpc_per_gpc = nvgpu_get_litter_value(g, | ||
283 | GPU_LIT_NUM_TPC_PER_GPC); | ||
284 | |||
285 | /* gv100 has 6 GPC and 7 TPC/GPC */ | ||
286 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { | ||
287 | for (pes = 0; pes < g->gr.pe_count_per_gpc; pes++) { | ||
288 | pes_tpc_mask |= (u64) g->gr.pes_tpc_mask[pes][gpc] << | ||
289 | (num_tpc_per_gpc * gpc); | ||
290 | } | ||
291 | } | ||
292 | |||
293 | nvgpu_log_info(g, "pes_tpc_mask: %016llx\n", pes_tpc_mask); | ||
294 | gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask)); | ||
295 | gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask)); | ||
296 | } | ||
297 | |||
298 | u32 gr_gv100_get_patch_slots(struct gk20a *g) | ||
299 | { | ||
300 | struct gr_gk20a *gr = &g->gr; | ||
301 | struct fifo_gk20a *f = &g->fifo; | ||
302 | u32 size = 0; | ||
303 | |||
304 | /* | ||
305 | * CMD to update PE table | ||
306 | */ | ||
307 | size++; | ||
308 | |||
309 | /* | ||
310 | * Update PE table contents | ||
311 | * for PE table, each patch buffer update writes 32 TPCs | ||
312 | */ | ||
313 | size += DIV_ROUND_UP(gr->tpc_count, 32); | ||
314 | |||
315 | /* | ||
316 | * Update the PL table contents | ||
317 | * For PL table, each patch buffer update configures 4 TPCs | ||
318 | */ | ||
319 | size += DIV_ROUND_UP(gr->tpc_count, 4); | ||
320 | |||
321 | /* | ||
322 | * We need this for all subcontexts | ||
323 | */ | ||
324 | size *= f->t19x.max_subctx_count; | ||
325 | |||
326 | /* | ||
327 | * Add space for a partition mode change as well | ||
328 | * reserve two slots since DYNAMIC -> STATIC requires | ||
329 | * DYNAMIC -> NONE -> STATIC | ||
330 | */ | ||
331 | size += 2; | ||
332 | |||
333 | /* | ||
334 | * Add current patch buffer size | ||
335 | */ | ||
336 | size += gr_gk20a_get_patch_slots(g); | ||
337 | |||
338 | /* | ||
339 | * Align to 4K size | ||
340 | */ | ||
341 | size = ALIGN(size, PATCH_CTX_SLOTS_PER_PAGE); | ||
342 | |||
343 | /* | ||
344 | * Increase the size to accommodate for additional TPC partition update | ||
345 | */ | ||
346 | size += 2 * PATCH_CTX_SLOTS_PER_PAGE; | ||
347 | |||
348 | return size; | ||
349 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h new file mode 100644 index 00000000..612f76f9 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * GV100 GPU GR | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GR_GV100_H_ | ||
26 | #define _NVGPU_GR_GV100_H_ | ||
27 | |||
28 | void gr_gv100_bundle_cb_defaults(struct gk20a *g); | ||
29 | void gr_gv100_cb_size_default(struct gk20a *g); | ||
30 | void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | ||
31 | void gr_gv100_init_sm_id_table(struct gk20a *g); | ||
32 | void gr_gv100_program_sm_id_numbering(struct gk20a *g, | ||
33 | u32 gpc, u32 tpc, u32 smid); | ||
34 | int gr_gv100_load_smid_config(struct gk20a *g); | ||
35 | u32 gr_gv100_get_patch_slots(struct gk20a *g); | ||
36 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h new file mode 100644 index 00000000..7cc1f77b --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gv100.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * GV100 Graphics | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef GV100_H | ||
26 | #define GV100_H | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | |||
30 | int gv100_init_gpu_characteristics(struct gk20a *g); | ||
31 | |||
32 | #endif /* GV11B_H */ | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c new file mode 100644 index 00000000..4044c4b5 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -0,0 +1,769 @@ | |||
1 | /* | ||
2 | * GV100 Tegra HAL interface | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <linux/types.h> | ||
26 | #include <linux/printk.h> | ||
27 | |||
28 | #include <linux/types.h> | ||
29 | #include <linux/tegra_gpu_t19x.h> | ||
30 | |||
31 | #include "gk20a/gk20a.h" | ||
32 | #include "gk20a/fifo_gk20a.h" | ||
33 | #include "gk20a/fecs_trace_gk20a.h" | ||
34 | #include "gk20a/css_gr_gk20a.h" | ||
35 | #include "gk20a/mc_gk20a.h" | ||
36 | #include "gk20a/dbg_gpu_gk20a.h" | ||
37 | #include "gk20a/bus_gk20a.h" | ||
38 | #include "gk20a/pramin_gk20a.h" | ||
39 | #include "gk20a/flcn_gk20a.h" | ||
40 | #include "gk20a/regops_gk20a.h" | ||
41 | #include "gk20a/fb_gk20a.h" | ||
42 | #include "gk20a/mm_gk20a.h" | ||
43 | #include "gk20a/pmu_gk20a.h" | ||
44 | #include "gk20a/gr_gk20a.h" | ||
45 | |||
46 | #include "gm20b/ltc_gm20b.h" | ||
47 | #include "gm20b/gr_gm20b.h" | ||
48 | #include "gm20b/fifo_gm20b.h" | ||
49 | #include "gm20b/fb_gm20b.h" | ||
50 | #include "gm20b/mm_gm20b.h" | ||
51 | #include "gm20b/pmu_gm20b.h" | ||
52 | #include "gm20b/acr_gm20b.h" | ||
53 | |||
54 | #include "gp10b/fb_gp10b.h" | ||
55 | #include "gp10b/gr_gp10b.h" | ||
56 | |||
57 | #include "gp106/clk_gp106.h" | ||
58 | #include "gp106/clk_arb_gp106.h" | ||
59 | #include "gp106/pmu_gp106.h" | ||
60 | #include "gp106/acr_gp106.h" | ||
61 | #include "gp106/sec2_gp106.h" | ||
62 | #include "gp106/bios_gp106.h" | ||
63 | #include "gv100/bios_gv100.h" | ||
64 | #include "gp106/therm_gp106.h" | ||
65 | #include "gp106/xve_gp106.h" | ||
66 | #include "gp106/clk_gp106.h" | ||
67 | #include "gp106/flcn_gp106.h" | ||
68 | #include "gp10b/ltc_gp10b.h" | ||
69 | #include "gp10b/therm_gp10b.h" | ||
70 | #include "gp10b/mc_gp10b.h" | ||
71 | #include "gp10b/ce_gp10b.h" | ||
72 | #include "gp10b/priv_ring_gp10b.h" | ||
73 | #include "gp10b/fifo_gp10b.h" | ||
74 | #include "gp10b/fecs_trace_gp10b.h" | ||
75 | #include "gp10b/mm_gp10b.h" | ||
76 | #include "gp10b/pmu_gp10b.h" | ||
77 | |||
78 | #include "gv11b/css_gr_gv11b.h" | ||
79 | #include "gv11b/dbg_gpu_gv11b.h" | ||
80 | #include "gv11b/hal_gv11b.h" | ||
81 | #include "gv100/gr_gv100.h" | ||
82 | #include "gv11b/mc_gv11b.h" | ||
83 | #include "gv11b/ltc_gv11b.h" | ||
84 | #include "gv11b/gv11b.h" | ||
85 | #include "gv11b/ce_gv11b.h" | ||
86 | #include "gv100/gr_ctx_gv100.h" | ||
87 | #include "gv11b/mm_gv11b.h" | ||
88 | #include "gv11b/pmu_gv11b.h" | ||
89 | #include "gv11b/fb_gv11b.h" | ||
90 | #include "gv100/mm_gv100.h" | ||
91 | #include "gv11b/pmu_gv11b.h" | ||
92 | #include "gv100/fb_gv100.h" | ||
93 | #include "gv100/fifo_gv100.h" | ||
94 | #include "gv11b/fifo_gv11b.h" | ||
95 | #include "gv11b/regops_gv11b.h" | ||
96 | |||
97 | #include "gv11b/gv11b_gating_reglist.h" | ||
98 | #include "gv100/regops_gv100.h" | ||
99 | #include "gv11b/subctx_gv11b.h" | ||
100 | |||
101 | #include "gv100.h" | ||
102 | #include "hal_gv100.h" | ||
103 | #include "gv100/fb_gv100.h" | ||
104 | #include "gv100/mm_gv100.h" | ||
105 | |||
106 | #include <nvgpu/bus.h> | ||
107 | #include <nvgpu/debug.h> | ||
108 | #include <nvgpu/enabled.h> | ||
109 | #include <nvgpu/enabled_t19x.h> | ||
110 | #include <nvgpu/ctxsw_trace.h> | ||
111 | |||
112 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | ||
113 | #include <nvgpu/hw/gv100/hw_fifo_gv100.h> | ||
114 | #include <nvgpu/hw/gv100/hw_ram_gv100.h> | ||
115 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | ||
116 | #include <nvgpu/hw/gv100/hw_pram_gv100.h> | ||
117 | #include <nvgpu/hw/gv100/hw_pwr_gv100.h> | ||
118 | |||
119 | static int gv100_get_litter_value(struct gk20a *g, int value) | ||
120 | { | ||
121 | int ret = EINVAL; | ||
122 | switch (value) { | ||
123 | case GPU_LIT_NUM_GPCS: | ||
124 | ret = proj_scal_litter_num_gpcs_v(); | ||
125 | break; | ||
126 | case GPU_LIT_NUM_PES_PER_GPC: | ||
127 | ret = proj_scal_litter_num_pes_per_gpc_v(); | ||
128 | break; | ||
129 | case GPU_LIT_NUM_ZCULL_BANKS: | ||
130 | ret = proj_scal_litter_num_zcull_banks_v(); | ||
131 | break; | ||
132 | case GPU_LIT_NUM_TPC_PER_GPC: | ||
133 | ret = proj_scal_litter_num_tpc_per_gpc_v(); | ||
134 | break; | ||
135 | case GPU_LIT_NUM_SM_PER_TPC: | ||
136 | ret = proj_scal_litter_num_sm_per_tpc_v(); | ||
137 | break; | ||
138 | case GPU_LIT_NUM_FBPS: | ||
139 | ret = proj_scal_litter_num_fbps_v(); | ||
140 | break; | ||
141 | case GPU_LIT_GPC_BASE: | ||
142 | ret = proj_gpc_base_v(); | ||
143 | break; | ||
144 | case GPU_LIT_GPC_STRIDE: | ||
145 | ret = proj_gpc_stride_v(); | ||
146 | break; | ||
147 | case GPU_LIT_GPC_SHARED_BASE: | ||
148 | ret = proj_gpc_shared_base_v(); | ||
149 | break; | ||
150 | case GPU_LIT_TPC_IN_GPC_BASE: | ||
151 | ret = proj_tpc_in_gpc_base_v(); | ||
152 | break; | ||
153 | case GPU_LIT_TPC_IN_GPC_STRIDE: | ||
154 | ret = proj_tpc_in_gpc_stride_v(); | ||
155 | break; | ||
156 | case GPU_LIT_TPC_IN_GPC_SHARED_BASE: | ||
157 | ret = proj_tpc_in_gpc_shared_base_v(); | ||
158 | break; | ||
159 | case GPU_LIT_PPC_IN_GPC_BASE: | ||
160 | ret = proj_ppc_in_gpc_base_v(); | ||
161 | break; | ||
162 | case GPU_LIT_PPC_IN_GPC_STRIDE: | ||
163 | ret = proj_ppc_in_gpc_stride_v(); | ||
164 | break; | ||
165 | case GPU_LIT_PPC_IN_GPC_SHARED_BASE: | ||
166 | ret = proj_ppc_in_gpc_shared_base_v(); | ||
167 | break; | ||
168 | case GPU_LIT_ROP_BASE: | ||
169 | ret = proj_rop_base_v(); | ||
170 | break; | ||
171 | case GPU_LIT_ROP_STRIDE: | ||
172 | ret = proj_rop_stride_v(); | ||
173 | break; | ||
174 | case GPU_LIT_ROP_SHARED_BASE: | ||
175 | ret = proj_rop_shared_base_v(); | ||
176 | break; | ||
177 | case GPU_LIT_HOST_NUM_ENGINES: | ||
178 | ret = proj_host_num_engines_v(); | ||
179 | break; | ||
180 | case GPU_LIT_HOST_NUM_PBDMA: | ||
181 | ret = proj_host_num_pbdma_v(); | ||
182 | break; | ||
183 | case GPU_LIT_LTC_STRIDE: | ||
184 | ret = proj_ltc_stride_v(); | ||
185 | break; | ||
186 | case GPU_LIT_LTS_STRIDE: | ||
187 | ret = proj_lts_stride_v(); | ||
188 | break; | ||
189 | case GPU_LIT_NUM_FBPAS: | ||
190 | ret = proj_scal_litter_num_fbpas_v(); | ||
191 | break; | ||
192 | case GPU_LIT_FBPA_SHARED_BASE: | ||
193 | ret = proj_fbpa_shared_base_v(); | ||
194 | break; | ||
195 | case GPU_LIT_FBPA_BASE: | ||
196 | ret = proj_fbpa_base_v(); | ||
197 | break; | ||
198 | case GPU_LIT_FBPA_STRIDE: | ||
199 | ret = proj_fbpa_stride_v(); | ||
200 | break; | ||
201 | case GPU_LIT_SM_PRI_STRIDE: | ||
202 | ret = proj_sm_stride_v(); | ||
203 | break; | ||
204 | case GPU_LIT_SMPC_PRI_BASE: | ||
205 | ret = proj_smpc_base_v(); | ||
206 | break; | ||
207 | case GPU_LIT_SMPC_PRI_SHARED_BASE: | ||
208 | ret = proj_smpc_shared_base_v(); | ||
209 | break; | ||
210 | case GPU_LIT_SMPC_PRI_UNIQUE_BASE: | ||
211 | ret = proj_smpc_unique_base_v(); | ||
212 | break; | ||
213 | case GPU_LIT_SMPC_PRI_STRIDE: | ||
214 | ret = proj_smpc_stride_v(); | ||
215 | break; | ||
216 | case GPU_LIT_TWOD_CLASS: | ||
217 | ret = FERMI_TWOD_A; | ||
218 | break; | ||
219 | case GPU_LIT_THREED_CLASS: | ||
220 | ret = VOLTA_A; | ||
221 | break; | ||
222 | case GPU_LIT_COMPUTE_CLASS: | ||
223 | ret = VOLTA_COMPUTE_A; | ||
224 | break; | ||
225 | case GPU_LIT_GPFIFO_CLASS: | ||
226 | ret = VOLTA_CHANNEL_GPFIFO_A; | ||
227 | break; | ||
228 | case GPU_LIT_I2M_CLASS: | ||
229 | ret = KEPLER_INLINE_TO_MEMORY_B; | ||
230 | break; | ||
231 | case GPU_LIT_DMA_COPY_CLASS: | ||
232 | ret = VOLTA_DMA_COPY_A; | ||
233 | break; | ||
234 | default: | ||
235 | break; | ||
236 | } | ||
237 | |||
238 | return ret; | ||
239 | } | ||
240 | |||
241 | int gv100_init_gpu_characteristics(struct gk20a *g) | ||
242 | { | ||
243 | int err; | ||
244 | |||
245 | err = gk20a_init_gpu_characteristics(g); | ||
246 | if (err) | ||
247 | return err; | ||
248 | |||
249 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); | ||
250 | |||
251 | return 0; | ||
252 | } | ||
253 | |||
254 | |||
255 | |||
256 | static const struct gpu_ops gv100_ops = { | ||
257 | .bios = { | ||
258 | .init = gp106_bios_init, | ||
259 | .preos_wait_for_halt = gv100_bios_preos_wait_for_halt, | ||
260 | .preos_reload_check = gv100_bios_preos_reload_check, | ||
261 | }, | ||
262 | .ltc = { | ||
263 | .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, | ||
264 | .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, | ||
265 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | ||
266 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | ||
267 | .init_cbc = NULL, | ||
268 | .init_fs_state = gv11b_ltc_init_fs_state, | ||
269 | .init_comptags = gp10b_ltc_init_comptags, | ||
270 | .cbc_ctrl = gm20b_ltc_cbc_ctrl, | ||
271 | .isr = gv11b_ltc_isr, | ||
272 | .cbc_fix_config = NULL, | ||
273 | .flush = gm20b_flush_ltc, | ||
274 | .set_enabled = gp10b_ltc_set_enabled, | ||
275 | }, | ||
276 | .ce2 = { | ||
277 | .isr_stall = gv11b_ce_isr, | ||
278 | .isr_nonstall = gp10b_ce_nonstall_isr, | ||
279 | .get_num_pce = gv11b_ce_get_num_pce, | ||
280 | }, | ||
281 | .gr = { | ||
282 | .get_patch_slots = gr_gv100_get_patch_slots, | ||
283 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | ||
284 | .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, | ||
285 | .cb_size_default = gr_gv100_cb_size_default, | ||
286 | .calc_global_ctx_buffer_size = | ||
287 | gr_gv11b_calc_global_ctx_buffer_size, | ||
288 | .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, | ||
289 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
290 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
291 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
292 | .handle_sw_method = gr_gv11b_handle_sw_method, | ||
293 | .set_alpha_circular_buffer_size = | ||
294 | gr_gv11b_set_alpha_circular_buffer_size, | ||
295 | .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, | ||
296 | .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, | ||
297 | .is_valid_class = gr_gv11b_is_valid_class, | ||
298 | .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, | ||
299 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | ||
300 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | ||
301 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | ||
302 | .init_fs_state = gr_gv11b_init_fs_state, | ||
303 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | ||
304 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
305 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, | ||
306 | .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, | ||
307 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | ||
308 | .free_channel_ctx = gk20a_free_channel_ctx, | ||
309 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | ||
310 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | ||
311 | .get_zcull_info = gr_gk20a_get_zcull_info, | ||
312 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
313 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
314 | .detect_sm_arch = gr_gv11b_detect_sm_arch, | ||
315 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
316 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
317 | .zbc_set_table = gk20a_gr_zbc_set_table, | ||
318 | .zbc_query_table = gr_gk20a_query_zbc, | ||
319 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
320 | .add_zbc = gr_gk20a_add_zbc, | ||
321 | .pagepool_default_size = gr_gv11b_pagepool_default_size, | ||
322 | .init_ctx_state = gr_gp10b_init_ctx_state, | ||
323 | .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, | ||
324 | .free_gr_ctx = gr_gp10b_free_gr_ctx, | ||
325 | .update_ctxsw_preemption_mode = | ||
326 | gr_gp10b_update_ctxsw_preemption_mode, | ||
327 | .dump_gr_regs = gr_gv11b_dump_gr_status_regs, | ||
328 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
329 | .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, | ||
330 | .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, | ||
331 | .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, | ||
332 | .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, | ||
333 | .get_max_fbps_count = gr_gm20b_get_max_fbps_count, | ||
334 | .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, | ||
335 | .wait_empty = gr_gv11b_wait_empty, | ||
336 | .init_cyclestats = gr_gm20b_init_cyclestats, | ||
337 | .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, | ||
338 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
339 | .bpt_reg_info = gv11b_gr_bpt_reg_info, | ||
340 | .get_access_map = gr_gv11b_get_access_map, | ||
341 | .handle_fecs_error = gr_gv11b_handle_fecs_error, | ||
342 | .handle_sm_exception = gr_gk20a_handle_sm_exception, | ||
343 | .handle_tex_exception = gr_gv11b_handle_tex_exception, | ||
344 | .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, | ||
345 | .enable_exceptions = gr_gv11b_enable_exceptions, | ||
346 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
347 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | ||
348 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | ||
349 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | ||
350 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | ||
351 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | ||
352 | .suspend_contexts = gr_gp10b_suspend_contexts, | ||
353 | .resume_contexts = gr_gk20a_resume_contexts, | ||
354 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
355 | .init_sm_id_table = gr_gv100_init_sm_id_table, | ||
356 | .load_smid_config = gr_gv11b_load_smid_config, | ||
357 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | ||
358 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
359 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
360 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
361 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
362 | .setup_rop_mapping = gr_gv11b_setup_rop_mapping, | ||
363 | .program_zcull_mapping = gr_gv11b_program_zcull_mapping, | ||
364 | .commit_global_timeslice = gr_gv11b_commit_global_timeslice, | ||
365 | .commit_inst = gr_gv11b_commit_inst, | ||
366 | .write_zcull_ptr = gr_gv11b_write_zcull_ptr, | ||
367 | .write_pm_ptr = gr_gv11b_write_pm_ptr, | ||
368 | .init_elcg_mode = gr_gv11b_init_elcg_mode, | ||
369 | .load_tpc_mask = gr_gv11b_load_tpc_mask, | ||
370 | .inval_icache = gr_gk20a_inval_icache, | ||
371 | .trigger_suspend = gv11b_gr_sm_trigger_suspend, | ||
372 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
373 | .resume_from_pause = gv11b_gr_resume_from_pause, | ||
374 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
375 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
376 | .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, | ||
377 | .sm_debugger_attached = gv11b_gr_sm_debugger_attached, | ||
378 | .suspend_single_sm = gv11b_gr_suspend_single_sm, | ||
379 | .suspend_all_sms = gv11b_gr_suspend_all_sms, | ||
380 | .resume_single_sm = gv11b_gr_resume_single_sm, | ||
381 | .resume_all_sms = gv11b_gr_resume_all_sms, | ||
382 | .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, | ||
383 | .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, | ||
384 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
385 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
386 | .lock_down_sm = gv11b_gr_lock_down_sm, | ||
387 | .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, | ||
388 | .clear_sm_hww = gv11b_gr_clear_sm_hww, | ||
389 | .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, | ||
390 | .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, | ||
391 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
392 | .set_boosted_ctx = gr_gp10b_set_boosted_ctx, | ||
393 | .set_preemption_mode = gr_gp10b_set_preemption_mode, | ||
394 | .set_czf_bypass = NULL, | ||
395 | .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, | ||
396 | .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, | ||
397 | .init_preemption_state = NULL, | ||
398 | .update_boosted_ctx = gr_gp10b_update_boosted_ctx, | ||
399 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
400 | .create_gr_sysfs = gr_gv11b_create_sysfs, | ||
401 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, | ||
402 | .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, | ||
403 | .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, | ||
404 | .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, | ||
405 | .zbc_s_query_table = gr_gv11b_zbc_s_query_table, | ||
406 | .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, | ||
407 | .handle_gpc_gpcmmu_exception = | ||
408 | gr_gv11b_handle_gpc_gpcmmu_exception, | ||
409 | .add_zbc_type_s = gr_gv11b_add_zbc_type_s, | ||
410 | .get_egpc_base = gv11b_gr_get_egpc_base, | ||
411 | .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, | ||
412 | .handle_gpc_gpccs_exception = | ||
413 | gr_gv11b_handle_gpc_gpccs_exception, | ||
414 | .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, | ||
415 | .access_smpc_reg = gv11b_gr_access_smpc_reg, | ||
416 | .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, | ||
417 | .add_zbc_s = gr_gv11b_add_zbc_stencil, | ||
418 | .handle_gcc_exception = gr_gv11b_handle_gcc_exception, | ||
419 | .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, | ||
420 | .handle_tpc_sm_ecc_exception = | ||
421 | gr_gv11b_handle_tpc_sm_ecc_exception, | ||
422 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | ||
423 | }, | ||
424 | .fb = { | ||
425 | .reset = gv100_fb_reset, | ||
426 | .init_hw = gk20a_fb_init_hw, | ||
427 | .init_fs_state = NULL, | ||
428 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
429 | .set_use_full_comp_tag_line = | ||
430 | gm20b_fb_set_use_full_comp_tag_line, | ||
431 | .compression_page_size = gp10b_fb_compression_page_size, | ||
432 | .compressible_page_size = gp10b_fb_compressible_page_size, | ||
433 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
434 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
435 | .read_wpr_info = gm20b_fb_read_wpr_info, | ||
436 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | ||
437 | .set_debug_mode = gm20b_fb_set_debug_mode, | ||
438 | .tlb_invalidate = gk20a_fb_tlb_invalidate, | ||
439 | .hub_isr = gv11b_fb_hub_isr, | ||
440 | .mem_unlock = gv100_fb_memory_unlock, | ||
441 | }, | ||
442 | .fifo = { | ||
443 | .get_preempt_timeout = gv100_fifo_get_preempt_timeout, | ||
444 | .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, | ||
445 | .bind_channel = channel_gm20b_bind, | ||
446 | .unbind_channel = channel_gv11b_unbind, | ||
447 | .disable_channel = gk20a_fifo_disable_channel, | ||
448 | .enable_channel = gk20a_fifo_enable_channel, | ||
449 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
450 | .free_inst = gk20a_fifo_free_inst, | ||
451 | .setup_ramfc = channel_gv11b_setup_ramfc, | ||
452 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
453 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
454 | .setup_userd = gk20a_fifo_setup_userd, | ||
455 | .userd_gp_get = gv11b_userd_gp_get, | ||
456 | .userd_gp_put = gv11b_userd_gp_put, | ||
457 | .userd_pb_get = gv11b_userd_pb_get, | ||
458 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
459 | .preempt_channel = gv11b_fifo_preempt_channel, | ||
460 | .preempt_tsg = gv11b_fifo_preempt_tsg, | ||
461 | .enable_tsg = gv11b_fifo_enable_tsg, | ||
462 | .disable_tsg = gk20a_disable_tsg, | ||
463 | .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, | ||
464 | .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, | ||
465 | .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, | ||
466 | .update_runlist = gk20a_fifo_update_runlist, | ||
467 | .trigger_mmu_fault = NULL, | ||
468 | .get_mmu_fault_info = NULL, | ||
469 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
470 | .get_num_fifos = gv100_fifo_get_num_fifos, | ||
471 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
472 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
473 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
474 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
475 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
476 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
477 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
478 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
479 | .runlist_entry_size = ram_rl_entry_size_v, | ||
480 | .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, | ||
481 | .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, | ||
482 | .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, | ||
483 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
484 | .dump_eng_status = gv11b_dump_eng_status, | ||
485 | .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, | ||
486 | .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, | ||
487 | .is_preempt_pending = gv11b_fifo_is_preempt_pending, | ||
488 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, | ||
489 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
490 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, | ||
491 | .handle_sched_error = gv11b_fifo_handle_sched_error, | ||
492 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, | ||
493 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, | ||
494 | .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, | ||
495 | .deinit_eng_method_buffers = | ||
496 | gv11b_fifo_deinit_eng_method_buffers, | ||
497 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
498 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
499 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
500 | .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, | ||
501 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, | ||
502 | .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, | ||
503 | .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, | ||
504 | .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, | ||
505 | .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, | ||
506 | #endif | ||
507 | .resetup_ramfc = NULL, | ||
508 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
509 | .free_channel_ctx_header = gv11b_free_subctx_header, | ||
510 | .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, | ||
511 | .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, | ||
512 | }, | ||
513 | .gr_ctx = { | ||
514 | .get_netlist_name = gr_gv100_get_netlist_name, | ||
515 | .is_fw_defined = gr_gv100_is_firmware_defined, | ||
516 | }, | ||
517 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
518 | .fecs_trace = { | ||
519 | .alloc_user_buffer = NULL, | ||
520 | .free_user_buffer = NULL, | ||
521 | .mmap_user_buffer = NULL, | ||
522 | .init = NULL, | ||
523 | .deinit = NULL, | ||
524 | .enable = NULL, | ||
525 | .disable = NULL, | ||
526 | .is_enabled = NULL, | ||
527 | .reset = NULL, | ||
528 | .flush = NULL, | ||
529 | .poll = NULL, | ||
530 | .bind_channel = NULL, | ||
531 | .unbind_channel = NULL, | ||
532 | .max_entries = NULL, | ||
533 | }, | ||
534 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | ||
535 | .mm = { | ||
536 | .support_sparse = gm20b_mm_support_sparse, | ||
537 | .gmmu_map = gk20a_locked_gmmu_map, | ||
538 | .gmmu_unmap = gk20a_locked_gmmu_unmap, | ||
539 | .vm_bind_channel = gk20a_vm_bind_channel, | ||
540 | .fb_flush = gk20a_mm_fb_flush, | ||
541 | .l2_invalidate = gk20a_mm_l2_invalidate, | ||
542 | .l2_flush = gk20a_mm_l2_flush, | ||
543 | .cbc_clean = gk20a_mm_cbc_clean, | ||
544 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
545 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
546 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | ||
547 | .gpu_phys_addr = gv11b_gpu_phys_addr, | ||
548 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | ||
549 | .get_vidmem_size = gv100_mm_get_vidmem_size, | ||
550 | .init_pdb = gp10b_mm_init_pdb, | ||
551 | .init_mm_setup_hw = gv11b_init_mm_setup_hw, | ||
552 | .is_bar1_supported = gv11b_mm_is_bar1_supported, | ||
553 | .alloc_inst_block = gk20a_alloc_inst_block, | ||
554 | .init_inst_block = gv11b_init_inst_block, | ||
555 | .mmu_fault_pending = gv11b_mm_mmu_fault_pending, | ||
556 | .get_kind_invalid = gm20b_get_kind_invalid, | ||
557 | .get_kind_pitch = gm20b_get_kind_pitch, | ||
558 | .init_bar2_vm = gb10b_init_bar2_vm, | ||
559 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, | ||
560 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, | ||
561 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | ||
562 | .get_flush_retries = gv100_mm_get_flush_retries, | ||
563 | }, | ||
564 | .pramin = { | ||
565 | .enter = gk20a_pramin_enter, | ||
566 | .exit = gk20a_pramin_exit, | ||
567 | .data032_r = pram_data032_r, | ||
568 | }, | ||
569 | .pmu = { | ||
570 | .init_wpr_region = gm20b_pmu_init_acr, | ||
571 | .load_lsfalcon_ucode = gp106_load_falcon_ucode, | ||
572 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, | ||
573 | .is_priv_load = gp106_is_priv_load, | ||
574 | .prepare_ucode = gp106_prepare_ucode_blob, | ||
575 | .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, | ||
576 | .get_wpr = gp106_wpr_info, | ||
577 | .alloc_blob_space = gp106_alloc_blob_space, | ||
578 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, | ||
579 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, | ||
580 | .falcon_wait_for_halt = sec2_wait_for_halt, | ||
581 | .falcon_clear_halt_interrupt_status = | ||
582 | sec2_clear_halt_interrupt_status, | ||
583 | .init_falcon_setup_hw = init_sec2_setup_hw1, | ||
584 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
585 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
586 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
587 | .is_pmu_supported = gp106_is_pmu_supported, | ||
588 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, | ||
589 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | ||
590 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
591 | .pmu_is_lpwr_feature_supported = | ||
592 | gp106_pmu_is_lpwr_feature_supported, | ||
593 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
594 | .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, | ||
595 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
596 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
597 | .pmu_pg_param_post_init = nvgpu_lpwr_post_init, | ||
598 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
599 | .pmu_pg_init_param = gp106_pg_param_init, | ||
600 | .reset_engine = gp106_pmu_engine_reset, | ||
601 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
602 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
603 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | ||
604 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
605 | }, | ||
606 | .clk = { | ||
607 | .init_clk_support = gp106_init_clk_support, | ||
608 | .get_crystal_clk_hz = gp106_crystal_clk_hz, | ||
609 | .measure_freq = gp106_clk_measure_freq, | ||
610 | .suspend_clk_support = gp106_suspend_clk_support, | ||
611 | }, | ||
612 | .clk_arb = { | ||
613 | .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, | ||
614 | .get_arbiter_clk_range = gp106_get_arbiter_clk_range, | ||
615 | .get_arbiter_clk_default = gp106_get_arbiter_clk_default, | ||
616 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | ||
617 | }, | ||
618 | .regops = { | ||
619 | .get_global_whitelist_ranges = | ||
620 | gv100_get_global_whitelist_ranges, | ||
621 | .get_global_whitelist_ranges_count = | ||
622 | gv100_get_global_whitelist_ranges_count, | ||
623 | .get_context_whitelist_ranges = | ||
624 | gv100_get_context_whitelist_ranges, | ||
625 | .get_context_whitelist_ranges_count = | ||
626 | gv100_get_context_whitelist_ranges_count, | ||
627 | .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, | ||
628 | .get_runcontrol_whitelist_count = | ||
629 | gv100_get_runcontrol_whitelist_count, | ||
630 | .get_runcontrol_whitelist_ranges = | ||
631 | gv100_get_runcontrol_whitelist_ranges, | ||
632 | .get_runcontrol_whitelist_ranges_count = | ||
633 | gv100_get_runcontrol_whitelist_ranges_count, | ||
634 | .get_qctl_whitelist = gv100_get_qctl_whitelist, | ||
635 | .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, | ||
636 | .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges, | ||
637 | .get_qctl_whitelist_ranges_count = | ||
638 | gv100_get_qctl_whitelist_ranges_count, | ||
639 | .apply_smpc_war = gv100_apply_smpc_war, | ||
640 | }, | ||
641 | .mc = { | ||
642 | .intr_enable = mc_gv11b_intr_enable, | ||
643 | .intr_unit_config = mc_gp10b_intr_unit_config, | ||
644 | .isr_stall = mc_gp10b_isr_stall, | ||
645 | .intr_stall = mc_gp10b_intr_stall, | ||
646 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | ||
647 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | ||
648 | .intr_nonstall = mc_gp10b_intr_nonstall, | ||
649 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | ||
650 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | ||
651 | .enable = gk20a_mc_enable, | ||
652 | .disable = gk20a_mc_disable, | ||
653 | .reset = gk20a_mc_reset, | ||
654 | .boot_0 = gk20a_mc_boot_0, | ||
655 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | ||
656 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, | ||
657 | }, | ||
658 | .debug = { | ||
659 | .show_dump = gk20a_debug_show_dump, | ||
660 | }, | ||
661 | .dbg_session_ops = { | ||
662 | .exec_reg_ops = exec_regops_gk20a, | ||
663 | .dbg_set_powergate = dbg_set_powergate, | ||
664 | .check_and_set_global_reservation = | ||
665 | nvgpu_check_and_set_global_reservation, | ||
666 | .check_and_set_context_reservation = | ||
667 | nvgpu_check_and_set_context_reservation, | ||
668 | .release_profiler_reservation = | ||
669 | nvgpu_release_profiler_reservation, | ||
670 | .perfbuffer_enable = gv11b_perfbuf_enable_locked, | ||
671 | .perfbuffer_disable = gv11b_perfbuf_disable_locked, | ||
672 | }, | ||
673 | .bus = { | ||
674 | .init_hw = gk20a_bus_init_hw, | ||
675 | .isr = gk20a_bus_isr, | ||
676 | .read_ptimer = gk20a_read_ptimer, | ||
677 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | ||
678 | .bar1_bind = NULL, | ||
679 | }, | ||
680 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
681 | .css = { | ||
682 | .enable_snapshot = gv11b_css_hw_enable_snapshot, | ||
683 | .disable_snapshot = gv11b_css_hw_disable_snapshot, | ||
684 | .check_data_available = gv11b_css_hw_check_data_available, | ||
685 | .set_handled_snapshots = css_hw_set_handled_snapshots, | ||
686 | .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, | ||
687 | .release_perfmon_ids = css_gr_release_perfmon_ids, | ||
688 | }, | ||
689 | #endif | ||
690 | .xve = { | ||
691 | .get_speed = xve_get_speed_gp106, | ||
692 | .set_speed = xve_set_speed_gp106, | ||
693 | .available_speeds = xve_available_speeds_gp106, | ||
694 | .xve_readl = xve_xve_readl_gp106, | ||
695 | .xve_writel = xve_xve_writel_gp106, | ||
696 | .disable_aspm = xve_disable_aspm_gp106, | ||
697 | .reset_gpu = xve_reset_gpu_gp106, | ||
698 | #if defined(CONFIG_PCI_MSI) | ||
699 | .rearm_msi = xve_rearm_msi_gp106, | ||
700 | #endif | ||
701 | .enable_shadow_rom = xve_enable_shadow_rom_gp106, | ||
702 | .disable_shadow_rom = xve_disable_shadow_rom_gp106, | ||
703 | }, | ||
704 | .falcon = { | ||
705 | .falcon_hal_sw_init = gp106_falcon_hal_sw_init, | ||
706 | }, | ||
707 | .priv_ring = { | ||
708 | .isr = gp10b_priv_ring_isr, | ||
709 | }, | ||
710 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, | ||
711 | .get_litter_value = gv100_get_litter_value, | ||
712 | }; | ||
713 | |||
714 | int gv100_init_hal(struct gk20a *g) | ||
715 | { | ||
716 | struct gpu_ops *gops = &g->ops; | ||
717 | |||
718 | gops->bios = gv100_ops.bios; | ||
719 | gops->ltc = gv100_ops.ltc; | ||
720 | gops->ce2 = gv100_ops.ce2; | ||
721 | gops->gr = gv100_ops.gr; | ||
722 | gops->fb = gv100_ops.fb; | ||
723 | gops->clock_gating = gv100_ops.clock_gating; | ||
724 | gops->fifo = gv100_ops.fifo; | ||
725 | gops->gr_ctx = gv100_ops.gr_ctx; | ||
726 | gops->mm = gv100_ops.mm; | ||
727 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
728 | gops->fecs_trace = gv100_ops.fecs_trace; | ||
729 | #endif | ||
730 | gops->pramin = gv100_ops.pramin; | ||
731 | gops->therm = gv100_ops.therm; | ||
732 | gops->pmu = gv100_ops.pmu; | ||
733 | gops->regops = gv100_ops.regops; | ||
734 | gops->mc = gv100_ops.mc; | ||
735 | gops->debug = gv100_ops.debug; | ||
736 | gops->dbg_session_ops = gv100_ops.dbg_session_ops; | ||
737 | gops->bus = gv100_ops.bus; | ||
738 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
739 | gops->css = gv100_ops.css; | ||
740 | #endif | ||
741 | gops->xve = gv100_ops.xve; | ||
742 | gops->falcon = gv100_ops.falcon; | ||
743 | gops->priv_ring = gv100_ops.priv_ring; | ||
744 | |||
745 | /* clocks */ | ||
746 | gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; | ||
747 | gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; | ||
748 | gops->clk.measure_freq = gv100_ops.clk.measure_freq; | ||
749 | gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; | ||
750 | |||
751 | /* Lone functions */ | ||
752 | gops->chip_init_gpu_characteristics = | ||
753 | gv100_ops.chip_init_gpu_characteristics; | ||
754 | gops->get_litter_value = gv100_ops.get_litter_value; | ||
755 | |||
756 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
757 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
758 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
759 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
760 | /* for now */ | ||
761 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | ||
762 | |||
763 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
764 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | ||
765 | |||
766 | g->name = "gv10x"; | ||
767 | |||
768 | return 0; | ||
769 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h new file mode 100644 index 00000000..7dcf1d77 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * GV100 Tegra HAL interface | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_HAL_GV11B_H | ||
26 | #define _NVGPU_HAL_GV11B_H | ||
27 | struct gk20a; | ||
28 | |||
29 | int gv100_init_hal(struct gk20a *gops); | ||
30 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c new file mode 100644 index 00000000..1b46faae --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c | |||
@@ -0,0 +1,55 @@ | |||
1 | /* | ||
2 | * GV100 memory management | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "gv100/mm_gv100.h" | ||
27 | |||
28 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> | ||
29 | |||
30 | size_t gv100_mm_get_vidmem_size(struct gk20a *g) | ||
31 | { | ||
32 | u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); | ||
33 | u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); | ||
34 | u32 scale = fb_mmu_local_memory_range_lower_scale_v(range); | ||
35 | u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range); | ||
36 | size_t bytes = ((size_t)mag << scale) * SZ_1M; | ||
37 | |||
38 | if (ecc) | ||
39 | bytes = bytes / 16 * 15; | ||
40 | |||
41 | return bytes; | ||
42 | } | ||
43 | |||
44 | u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op) | ||
45 | { | ||
46 | switch (op) { | ||
47 | /* GV100 has a large FB so it needs larger timeouts */ | ||
48 | case NVGPU_FLUSH_FB: | ||
49 | return 2000; | ||
50 | case NVGPU_FLUSH_L2_FLUSH: | ||
51 | return 2000; | ||
52 | default: | ||
53 | return 200; /* Default retry timer */ | ||
54 | } | ||
55 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h new file mode 100644 index 00000000..ea896503 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * GV100 memory management | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef MM_GV100_H | ||
26 | #define MM_GV100_H | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | size_t gv100_mm_get_vidmem_size(struct gk20a *g); | ||
31 | u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op); | ||
32 | |||
33 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c new file mode 100644 index 00000000..00f05418 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c | |||
@@ -0,0 +1,463 @@ | |||
1 | /* | ||
2 | * Tegra GV100 GPU Driver Register Ops | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | ||
28 | #include "regops_gv100.h" | ||
29 | |||
30 | static const struct regop_offset_range gv100_global_whitelist_ranges[] = { | ||
31 | { 0x000004f0, 1}, | ||
32 | { 0x00001a00, 3}, | ||
33 | { 0x00002800, 128}, | ||
34 | { 0x00009400, 1}, | ||
35 | { 0x00009410, 1}, | ||
36 | { 0x00009480, 1}, | ||
37 | { 0x00020200, 24}, | ||
38 | { 0x00021c00, 4}, | ||
39 | { 0x00021c14, 3}, | ||
40 | { 0x00021c24, 1}, | ||
41 | { 0x00021c2c, 69}, | ||
42 | { 0x00021d44, 1}, | ||
43 | { 0x00021d4c, 1}, | ||
44 | { 0x00021d54, 1}, | ||
45 | { 0x00021d5c, 1}, | ||
46 | { 0x00021d64, 2}, | ||
47 | { 0x00021d70, 16}, | ||
48 | { 0x00022430, 7}, | ||
49 | { 0x00022450, 1}, | ||
50 | { 0x0002245c, 2}, | ||
51 | { 0x00070000, 5}, | ||
52 | { 0x000884e0, 1}, | ||
53 | { 0x0008e00c, 1}, | ||
54 | { 0x00100c18, 3}, | ||
55 | { 0x00100c84, 1}, | ||
56 | { 0x00104038, 1}, | ||
57 | { 0x0010a0a8, 1}, | ||
58 | { 0x0010a4f0, 1}, | ||
59 | { 0x0010e490, 1}, | ||
60 | { 0x0013cc14, 1}, | ||
61 | { 0x00140028, 1}, | ||
62 | { 0x00140280, 1}, | ||
63 | { 0x001402a0, 1}, | ||
64 | { 0x00140350, 1}, | ||
65 | { 0x00140480, 1}, | ||
66 | { 0x001404a0, 1}, | ||
67 | { 0x00140550, 1}, | ||
68 | { 0x00142028, 1}, | ||
69 | { 0x00142280, 1}, | ||
70 | { 0x001422a0, 1}, | ||
71 | { 0x00142350, 1}, | ||
72 | { 0x00142480, 1}, | ||
73 | { 0x001424a0, 1}, | ||
74 | { 0x00142550, 1}, | ||
75 | { 0x0017e028, 1}, | ||
76 | { 0x0017e280, 1}, | ||
77 | { 0x0017e294, 1}, | ||
78 | { 0x0017e29c, 2}, | ||
79 | { 0x0017e2ac, 1}, | ||
80 | { 0x0017e350, 1}, | ||
81 | { 0x0017e39c, 1}, | ||
82 | { 0x0017e480, 1}, | ||
83 | { 0x0017e4a0, 1}, | ||
84 | { 0x0017e550, 1}, | ||
85 | { 0x00180040, 41}, | ||
86 | { 0x001800ec, 10}, | ||
87 | { 0x00180240, 41}, | ||
88 | { 0x001802ec, 10}, | ||
89 | { 0x00180440, 41}, | ||
90 | { 0x001804ec, 10}, | ||
91 | { 0x00180640, 41}, | ||
92 | { 0x001806ec, 10}, | ||
93 | { 0x00180840, 41}, | ||
94 | { 0x001808ec, 10}, | ||
95 | { 0x00180a40, 41}, | ||
96 | { 0x00180aec, 10}, | ||
97 | { 0x00180c40, 41}, | ||
98 | { 0x00180cec, 10}, | ||
99 | { 0x00180e40, 41}, | ||
100 | { 0x00180eec, 10}, | ||
101 | { 0x001a0040, 41}, | ||
102 | { 0x001a00ec, 10}, | ||
103 | { 0x001a0240, 41}, | ||
104 | { 0x001a02ec, 10}, | ||
105 | { 0x001a0440, 41}, | ||
106 | { 0x001a04ec, 10}, | ||
107 | { 0x001a0640, 41}, | ||
108 | { 0x001a06ec, 10}, | ||
109 | { 0x001a0840, 41}, | ||
110 | { 0x001a08ec, 10}, | ||
111 | { 0x001a0a40, 41}, | ||
112 | { 0x001a0aec, 10}, | ||
113 | { 0x001a0c40, 41}, | ||
114 | { 0x001a0cec, 10}, | ||
115 | { 0x001a0e40, 41}, | ||
116 | { 0x001a0eec, 10}, | ||
117 | { 0x001b0040, 41}, | ||
118 | { 0x001b00ec, 10}, | ||
119 | { 0x001b0240, 41}, | ||
120 | { 0x001b02ec, 10}, | ||
121 | { 0x001b0440, 41}, | ||
122 | { 0x001b04ec, 10}, | ||
123 | { 0x001b0640, 41}, | ||
124 | { 0x001b06ec, 10}, | ||
125 | { 0x001b0840, 41}, | ||
126 | { 0x001b08ec, 10}, | ||
127 | { 0x001b0a40, 41}, | ||
128 | { 0x001b0aec, 10}, | ||
129 | { 0x001b0c40, 41}, | ||
130 | { 0x001b0cec, 10}, | ||
131 | { 0x001b0e40, 41}, | ||
132 | { 0x001b0eec, 10}, | ||
133 | { 0x001b4000, 1}, | ||
134 | { 0x001b4008, 1}, | ||
135 | { 0x001b4010, 3}, | ||
136 | { 0x001b4020, 3}, | ||
137 | { 0x001b4030, 3}, | ||
138 | { 0x001b4040, 3}, | ||
139 | { 0x001b4050, 3}, | ||
140 | { 0x001b4060, 4}, | ||
141 | { 0x001b4074, 7}, | ||
142 | { 0x001b4094, 3}, | ||
143 | { 0x001b40a4, 1}, | ||
144 | { 0x001b4100, 6}, | ||
145 | { 0x001b4128, 1}, | ||
146 | { 0x001b8000, 1}, | ||
147 | { 0x001b8008, 1}, | ||
148 | { 0x001b8010, 2}, | ||
149 | { 0x001bc000, 1}, | ||
150 | { 0x001bc008, 1}, | ||
151 | { 0x001bc010, 2}, | ||
152 | { 0x001be000, 1}, | ||
153 | { 0x001be008, 1}, | ||
154 | { 0x001be010, 2}, | ||
155 | { 0x00400500, 1}, | ||
156 | { 0x0040415c, 1}, | ||
157 | { 0x00404468, 1}, | ||
158 | { 0x00404498, 1}, | ||
159 | { 0x00405800, 1}, | ||
160 | { 0x00405840, 2}, | ||
161 | { 0x00405850, 1}, | ||
162 | { 0x00405908, 1}, | ||
163 | { 0x00405b40, 1}, | ||
164 | { 0x00405b50, 1}, | ||
165 | { 0x00406024, 5}, | ||
166 | { 0x00407010, 1}, | ||
167 | { 0x00407808, 1}, | ||
168 | { 0x0040803c, 1}, | ||
169 | { 0x00408804, 1}, | ||
170 | { 0x0040880c, 1}, | ||
171 | { 0x00408900, 2}, | ||
172 | { 0x00408910, 1}, | ||
173 | { 0x00408944, 1}, | ||
174 | { 0x00408984, 1}, | ||
175 | { 0x004090a8, 1}, | ||
176 | { 0x004098a0, 1}, | ||
177 | { 0x00409b00, 1}, | ||
178 | { 0x0041000c, 1}, | ||
179 | { 0x00410110, 1}, | ||
180 | { 0x00410184, 1}, | ||
181 | { 0x0041040c, 1}, | ||
182 | { 0x00410510, 1}, | ||
183 | { 0x00410584, 1}, | ||
184 | { 0x00418000, 1}, | ||
185 | { 0x00418008, 1}, | ||
186 | { 0x00418380, 2}, | ||
187 | { 0x00418400, 2}, | ||
188 | { 0x004184a0, 1}, | ||
189 | { 0x00418604, 1}, | ||
190 | { 0x00418680, 1}, | ||
191 | { 0x00418704, 1}, | ||
192 | { 0x00418714, 1}, | ||
193 | { 0x00418800, 1}, | ||
194 | { 0x0041881c, 1}, | ||
195 | { 0x00418830, 1}, | ||
196 | { 0x00418884, 1}, | ||
197 | { 0x004188b0, 1}, | ||
198 | { 0x004188c8, 3}, | ||
199 | { 0x004188fc, 1}, | ||
200 | { 0x00418b04, 1}, | ||
201 | { 0x00418c04, 1}, | ||
202 | { 0x00418c10, 8}, | ||
203 | { 0x00418c88, 1}, | ||
204 | { 0x00418d00, 1}, | ||
205 | { 0x00418e00, 1}, | ||
206 | { 0x00418e08, 1}, | ||
207 | { 0x00418e34, 1}, | ||
208 | { 0x00418e40, 4}, | ||
209 | { 0x00418e58, 16}, | ||
210 | { 0x00418f08, 1}, | ||
211 | { 0x00419000, 1}, | ||
212 | { 0x0041900c, 1}, | ||
213 | { 0x00419018, 1}, | ||
214 | { 0x00419854, 1}, | ||
215 | { 0x00419864, 1}, | ||
216 | { 0x00419a04, 2}, | ||
217 | { 0x00419a14, 1}, | ||
218 | { 0x00419ab0, 1}, | ||
219 | { 0x00419ab8, 3}, | ||
220 | { 0x00419c0c, 1}, | ||
221 | { 0x00419c8c, 2}, | ||
222 | { 0x00419d00, 1}, | ||
223 | { 0x00419d08, 2}, | ||
224 | { 0x00419e00, 11}, | ||
225 | { 0x00419e34, 2}, | ||
226 | { 0x00419e44, 11}, | ||
227 | { 0x00419e74, 10}, | ||
228 | { 0x00419ea4, 1}, | ||
229 | { 0x00419eac, 2}, | ||
230 | { 0x00419ee8, 1}, | ||
231 | { 0x00419ef0, 28}, | ||
232 | { 0x00419f70, 1}, | ||
233 | { 0x00419f78, 2}, | ||
234 | { 0x00419f98, 2}, | ||
235 | { 0x0041a02c, 2}, | ||
236 | { 0x0041a0a8, 1}, | ||
237 | { 0x0041a8a0, 3}, | ||
238 | { 0x0041b014, 1}, | ||
239 | { 0x0041b0a0, 1}, | ||
240 | { 0x0041b0cc, 1}, | ||
241 | { 0x0041b1dc, 1}, | ||
242 | { 0x0041be0c, 3}, | ||
243 | { 0x0041bea0, 1}, | ||
244 | { 0x0041becc, 1}, | ||
245 | { 0x0041bfdc, 1}, | ||
246 | { 0x0041c054, 1}, | ||
247 | { 0x0041c2b0, 1}, | ||
248 | { 0x0041c2b8, 3}, | ||
249 | { 0x0041c40c, 1}, | ||
250 | { 0x0041c48c, 2}, | ||
251 | { 0x0041c500, 1}, | ||
252 | { 0x0041c508, 2}, | ||
253 | { 0x0041c600, 11}, | ||
254 | { 0x0041c634, 2}, | ||
255 | { 0x0041c644, 11}, | ||
256 | { 0x0041c674, 10}, | ||
257 | { 0x0041c6a4, 1}, | ||
258 | { 0x0041c6ac, 2}, | ||
259 | { 0x0041c6e8, 1}, | ||
260 | { 0x0041c6f0, 28}, | ||
261 | { 0x0041c770, 1}, | ||
262 | { 0x0041c778, 2}, | ||
263 | { 0x0041c798, 2}, | ||
264 | { 0x0041c854, 1}, | ||
265 | { 0x0041cab0, 1}, | ||
266 | { 0x0041cab8, 3}, | ||
267 | { 0x0041cc0c, 1}, | ||
268 | { 0x0041cc8c, 2}, | ||
269 | { 0x0041cd00, 1}, | ||
270 | { 0x0041cd08, 2}, | ||
271 | { 0x0041ce00, 11}, | ||
272 | { 0x0041ce34, 2}, | ||
273 | { 0x0041ce44, 11}, | ||
274 | { 0x0041ce74, 10}, | ||
275 | { 0x0041cea4, 1}, | ||
276 | { 0x0041ceac, 2}, | ||
277 | { 0x0041cee8, 1}, | ||
278 | { 0x0041cef0, 28}, | ||
279 | { 0x0041cf70, 1}, | ||
280 | { 0x0041cf78, 2}, | ||
281 | { 0x0041cf98, 2}, | ||
282 | { 0x00500384, 1}, | ||
283 | { 0x005004a0, 1}, | ||
284 | { 0x00500604, 1}, | ||
285 | { 0x00500680, 1}, | ||
286 | { 0x00500714, 1}, | ||
287 | { 0x0050081c, 1}, | ||
288 | { 0x00500884, 1}, | ||
289 | { 0x005008b0, 1}, | ||
290 | { 0x005008c8, 3}, | ||
291 | { 0x005008fc, 1}, | ||
292 | { 0x00500b04, 1}, | ||
293 | { 0x00500c04, 1}, | ||
294 | { 0x00500c10, 8}, | ||
295 | { 0x00500c88, 1}, | ||
296 | { 0x00500d00, 1}, | ||
297 | { 0x00500e08, 1}, | ||
298 | { 0x00500f08, 1}, | ||
299 | { 0x00501000, 1}, | ||
300 | { 0x0050100c, 1}, | ||
301 | { 0x00501018, 1}, | ||
302 | { 0x00501854, 1}, | ||
303 | { 0x00501ab0, 1}, | ||
304 | { 0x00501ab8, 3}, | ||
305 | { 0x00501c0c, 1}, | ||
306 | { 0x00501c8c, 2}, | ||
307 | { 0x00501d00, 1}, | ||
308 | { 0x00501d08, 2}, | ||
309 | { 0x00501e00, 11}, | ||
310 | { 0x00501e34, 2}, | ||
311 | { 0x00501e44, 11}, | ||
312 | { 0x00501e74, 10}, | ||
313 | { 0x00501ea4, 1}, | ||
314 | { 0x00501eac, 2}, | ||
315 | { 0x00501ee8, 1}, | ||
316 | { 0x00501ef0, 28}, | ||
317 | { 0x00501f70, 1}, | ||
318 | { 0x00501f78, 2}, | ||
319 | { 0x00501f98, 2}, | ||
320 | { 0x0050202c, 2}, | ||
321 | { 0x005020a8, 1}, | ||
322 | { 0x005028a0, 3}, | ||
323 | { 0x00503014, 1}, | ||
324 | { 0x005030a0, 1}, | ||
325 | { 0x005030cc, 1}, | ||
326 | { 0x005031dc, 1}, | ||
327 | { 0x00503e14, 1}, | ||
328 | { 0x00503ea0, 1}, | ||
329 | { 0x00503ecc, 1}, | ||
330 | { 0x00503fdc, 1}, | ||
331 | { 0x00504054, 1}, | ||
332 | { 0x005042b0, 1}, | ||
333 | { 0x005042b8, 3}, | ||
334 | { 0x0050440c, 1}, | ||
335 | { 0x0050448c, 2}, | ||
336 | { 0x00504500, 1}, | ||
337 | { 0x00504508, 2}, | ||
338 | { 0x00504600, 11}, | ||
339 | { 0x00504634, 2}, | ||
340 | { 0x00504644, 11}, | ||
341 | { 0x00504674, 10}, | ||
342 | { 0x005046a4, 1}, | ||
343 | { 0x005046ac, 2}, | ||
344 | { 0x005046e8, 1}, | ||
345 | { 0x005046f0, 28}, | ||
346 | { 0x00504770, 1}, | ||
347 | { 0x00504778, 2}, | ||
348 | { 0x00504798, 2}, | ||
349 | { 0x00504854, 1}, | ||
350 | { 0x00504ab0, 1}, | ||
351 | { 0x00504ab8, 3}, | ||
352 | { 0x00504c0c, 1}, | ||
353 | { 0x00504c8c, 2}, | ||
354 | { 0x00504d00, 1}, | ||
355 | { 0x00504d08, 2}, | ||
356 | { 0x00504e00, 11}, | ||
357 | { 0x00504e34, 2}, | ||
358 | { 0x00504e44, 11}, | ||
359 | { 0x00504e74, 10}, | ||
360 | { 0x00504ea4, 1}, | ||
361 | { 0x00504eac, 2}, | ||
362 | { 0x00504ee8, 1}, | ||
363 | { 0x00504ef0, 28}, | ||
364 | { 0x00504f70, 1}, | ||
365 | { 0x00504f78, 2}, | ||
366 | { 0x00504f98, 2}, | ||
367 | { 0x00900100, 1}, | ||
368 | { 0x009a0100, 1},}; | ||
369 | |||
370 | |||
371 | static const u32 gv100_global_whitelist_ranges_count = | ||
372 | ARRAY_SIZE(gv100_global_whitelist_ranges); | ||
373 | |||
374 | /* context */ | ||
375 | |||
376 | /* runcontrol */ | ||
377 | static const u32 gv100_runcontrol_whitelist[] = { | ||
378 | }; | ||
379 | static const u32 gv100_runcontrol_whitelist_count = | ||
380 | ARRAY_SIZE(gv100_runcontrol_whitelist); | ||
381 | |||
382 | static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = { | ||
383 | }; | ||
384 | static const u32 gv100_runcontrol_whitelist_ranges_count = | ||
385 | ARRAY_SIZE(gv100_runcontrol_whitelist_ranges); | ||
386 | |||
387 | |||
388 | /* quad ctl */ | ||
389 | static const u32 gv100_qctl_whitelist[] = { | ||
390 | }; | ||
391 | static const u32 gv100_qctl_whitelist_count = | ||
392 | ARRAY_SIZE(gv100_qctl_whitelist); | ||
393 | |||
394 | static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = { | ||
395 | }; | ||
396 | static const u32 gv100_qctl_whitelist_ranges_count = | ||
397 | ARRAY_SIZE(gv100_qctl_whitelist_ranges); | ||
398 | |||
399 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) | ||
400 | { | ||
401 | return gv100_global_whitelist_ranges; | ||
402 | } | ||
403 | |||
404 | int gv100_get_global_whitelist_ranges_count(void) | ||
405 | { | ||
406 | return gv100_global_whitelist_ranges_count; | ||
407 | } | ||
408 | |||
409 | const struct regop_offset_range *gv100_get_context_whitelist_ranges(void) | ||
410 | { | ||
411 | return gv100_global_whitelist_ranges; | ||
412 | } | ||
413 | |||
414 | int gv100_get_context_whitelist_ranges_count(void) | ||
415 | { | ||
416 | return gv100_global_whitelist_ranges_count; | ||
417 | } | ||
418 | |||
419 | const u32 *gv100_get_runcontrol_whitelist(void) | ||
420 | { | ||
421 | return gv100_runcontrol_whitelist; | ||
422 | } | ||
423 | |||
424 | int gv100_get_runcontrol_whitelist_count(void) | ||
425 | { | ||
426 | return gv100_runcontrol_whitelist_count; | ||
427 | } | ||
428 | |||
429 | const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void) | ||
430 | { | ||
431 | return gv100_runcontrol_whitelist_ranges; | ||
432 | } | ||
433 | |||
434 | int gv100_get_runcontrol_whitelist_ranges_count(void) | ||
435 | { | ||
436 | return gv100_runcontrol_whitelist_ranges_count; | ||
437 | } | ||
438 | |||
439 | const u32 *gv100_get_qctl_whitelist(void) | ||
440 | { | ||
441 | return gv100_qctl_whitelist; | ||
442 | } | ||
443 | |||
444 | int gv100_get_qctl_whitelist_count(void) | ||
445 | { | ||
446 | return gv100_qctl_whitelist_count; | ||
447 | } | ||
448 | |||
449 | const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void) | ||
450 | { | ||
451 | return gv100_qctl_whitelist_ranges; | ||
452 | } | ||
453 | |||
454 | int gv100_get_qctl_whitelist_ranges_count(void) | ||
455 | { | ||
456 | return gv100_qctl_whitelist_ranges_count; | ||
457 | } | ||
458 | |||
459 | int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
460 | { | ||
461 | /* Not needed on gv100 */ | ||
462 | return 0; | ||
463 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.h b/drivers/gpu/nvgpu/gv100/regops_gv100.h new file mode 100644 index 00000000..06e5b8e1 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Tegra GV100 GPU Driver Register Ops | ||
4 | * | ||
5 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
6 | * | ||
7 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
8 | * copy of this software and associated documentation files (the "Software"), | ||
9 | * to deal in the Software without restriction, including without limitation | ||
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
11 | * and/or sell copies of the Software, and to permit persons to whom the | ||
12 | * Software is furnished to do so, subject to the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice shall be included in | ||
15 | * all copies or substantial portions of the Software. | ||
16 | * | ||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
23 | * DEALINGS IN THE SOFTWARE. | ||
24 | */ | ||
25 | #ifndef __REGOPS_GV100_H_ | ||
26 | #define __REGOPS_GV100_H_ | ||
27 | |||
28 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void); | ||
29 | int gv100_get_global_whitelist_ranges_count(void); | ||
30 | const struct regop_offset_range *gv100_get_context_whitelist_ranges(void); | ||
31 | int gv100_get_context_whitelist_ranges_count(void); | ||
32 | const u32 *gv100_get_runcontrol_whitelist(void); | ||
33 | int gv100_get_runcontrol_whitelist_count(void); | ||
34 | const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void); | ||
35 | int gv100_get_runcontrol_whitelist_ranges_count(void); | ||
36 | const u32 *gv100_get_qctl_whitelist(void); | ||
37 | int gv100_get_qctl_whitelist_count(void); | ||
38 | const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void); | ||
39 | int gv100_get_qctl_whitelist_ranges_count(void); | ||
40 | int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | ||
41 | |||
42 | #endif /* __REGOPS_GV11B_H_ */ | ||