From de8e057f7eebcfe676278826ab457bf86b1b36fd Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: GV100 support Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 58 +++++ drivers/gpu/nvgpu/gv100/fb_gv100.h | 22 ++ drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 38 +++ drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | 28 +++ drivers/gpu/nvgpu/gv100/gv100.h | 26 ++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 441 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/hal_gv100.h | 21 ++ drivers/gpu/nvgpu/gv100/mm_gv100.c | 41 +++ drivers/gpu/nvgpu/gv100/mm_gv100.h | 23 ++ 9 files changed, 698 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.h (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c new file mode 100644 index 00000000..a3785266 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -0,0 +1,58 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gv11b/fb_gv11b.h" +#include "gv100/fb_gv100.h" + +#include + +#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ +#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ + +static void gv100_fb_reset(struct gk20a *g) +{ + u32 val; + int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; + + nvgpu_info(g, "reset gv100 fb"); + + /* wait for memory to be accessible */ + do { + u32 w = gk20a_readl(g, fb_niso_scrub_status_r()); + if (fb_niso_scrub_status_flag_v(w)) { + nvgpu_info(g, "done"); + break; + } + nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT); + } while (--retries); + + val = gk20a_readl(g, fb_mmu_priv_level_mask_r()); + val &= ~fb_mmu_priv_level_mask_write_violation_m(); + gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); +} + +void gv100_init_fb(struct gpu_ops *gops) +{ + gv11b_init_fb(gops); + gops->fb.reset = gv100_fb_reset; +} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h new file mode 100644 index 00000000..b234fa13 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -0,0 +1,22 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GV100_FB +#define _NVGPU_GV100_FB + +struct gpu_ops; + +void gv100_init_fb(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c new file mode 100644 index 00000000..2e605cce --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -0,0 +1,38 @@ +/* + * GV100 Graphics Context + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gr_ctx_gv100.h" + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name) +{ + u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; + + switch (ver) { + case NVGPU_GPUID_GV100: + sprintf(name, "%s/%s", "gv100", + GV100_NETLIST_IMAGE_FW_NAME); + break; + default: + nvgpu_err(g, "no support for GPUID %x", ver); + } + + return 0; +} + +bool gr_gv100_is_firmware_defined(void) +{ + return true; +} diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h new file mode 100644 index 00000000..122e750f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __GR_CTX_GV100_H__ +#define __GR_CTX_GV100_H__ + +#include "gk20a/gr_ctx_gk20a.h" +#include "nvgpu_gpuid_t19x.h" + +/* production netlist, one and only one from below */ +#define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name); +bool gr_gv100_is_firmware_defined(void); + +#endif /*__GR_CTX_GV100_H__*/ diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h new file mode 100644 index 00000000..eeea64a4 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gv100.h @@ -0,0 +1,26 @@ +/* + * GV100 Graphics + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef GV100_H +#define GV100_H + +#include "gk20a/gk20a.h" + +int gv100_init_gpu_characteristics(struct gk20a *g); + +#endif /* GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c new file mode 100644 index 00000000..337c607f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -0,0 +1,441 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/fecs_trace_gk20a.h" +#include "gk20a/css_gr_gk20a.h" +#include "gk20a/mc_gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/bus_gk20a.h" +#include "gk20a/pramin_gk20a.h" +#include "gk20a/flcn_gk20a.h" +#include "gk20a/regops_gk20a.h" + +#include "gm20b/ltc_gm20b.h" +#include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" + +#include "gp106/clk_gp106.h" +#include "gp106/clk_arb_gp106.h" +#include "gp106/pmu_gp106.h" + +#include "gm206/bios_gm206.h" +#include "gp106/therm_gp106.h" +#include "gp106/xve_gp106.h" +#include "gp106/clk_gp106.h" +#include "gp106/flcn_gp106.h" +#include "gp10b/ltc_gp10b.h" +#include "gp10b/therm_gp10b.h" +#include "gp10b/mc_gp10b.h" +#include "gp10b/ce_gp10b.h" +#include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fifo_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" + +#include "gv11b/hal_gv11b.h" +#include "gv11b/gr_gv11b.h" +#include "gv11b/mc_gv11b.h" +#include "gv11b/ltc_gv11b.h" +#include "gv11b/gv11b.h" +#include "gv11b/ce_gv11b.h" +#include "gv100/gr_ctx_gv100.h" +#include "gv100/mm_gv100.h" +#include "gv11b/pmu_gv11b.h" +#include "gv100/fb_gv100.h" +#include "gv11b/fifo_gv11b.h" +#include "gv11b/gv11b_gating_reglist.h" +#include "gv11b/regops_gv11b.h" +#include "gv11b/subctx_gv11b.h" + +#include "gv100.h" +#include "hal_gv100.h" + +#include +#include + +#include +#include +#include +#include +#include + +static int gv100_get_litter_value(struct gk20a *g, int value) +{ + int ret = EINVAL; + switch (value) { + case GPU_LIT_NUM_GPCS: + ret = proj_scal_litter_num_gpcs_v(); + break; + case GPU_LIT_NUM_PES_PER_GPC: + ret = proj_scal_litter_num_pes_per_gpc_v(); + break; + case GPU_LIT_NUM_ZCULL_BANKS: + ret = proj_scal_litter_num_zcull_banks_v(); + break; + case GPU_LIT_NUM_TPC_PER_GPC: + ret = proj_scal_litter_num_tpc_per_gpc_v(); + break; + case GPU_LIT_NUM_SM_PER_TPC: + ret = proj_scal_litter_num_sm_per_tpc_v(); + break; + case GPU_LIT_NUM_FBPS: + ret = proj_scal_litter_num_fbps_v(); + break; + case GPU_LIT_GPC_BASE: + ret = proj_gpc_base_v(); + break; + case GPU_LIT_GPC_STRIDE: + ret = proj_gpc_stride_v(); + break; + case GPU_LIT_GPC_SHARED_BASE: + ret = proj_gpc_shared_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_BASE: + ret = proj_tpc_in_gpc_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_STRIDE: + ret = proj_tpc_in_gpc_stride_v(); + break; + case GPU_LIT_TPC_IN_GPC_SHARED_BASE: + ret = proj_tpc_in_gpc_shared_base_v(); + break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + case GPU_LIT_PPC_IN_GPC_STRIDE: + ret = proj_ppc_in_gpc_stride_v(); + break; + case GPU_LIT_ROP_BASE: + ret = proj_rop_base_v(); + break; + case GPU_LIT_ROP_STRIDE: + ret = proj_rop_stride_v(); + break; + case GPU_LIT_ROP_SHARED_BASE: + ret = proj_rop_shared_base_v(); + break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; + case GPU_LIT_HOST_NUM_PBDMA: + ret = proj_host_num_pbdma_v(); + break; + case GPU_LIT_LTC_STRIDE: + ret = proj_ltc_stride_v(); + break; + case GPU_LIT_LTS_STRIDE: + ret = proj_lts_stride_v(); + break; + case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + case GPU_LIT_FBPA_STRIDE: + ret = proj_fbpa_stride_v(); + break; + case GPU_LIT_SM_PRI_STRIDE: + ret = proj_sm_stride_v(); + break; + + default: + break; + } + + return ret; +} + +int gv100_init_gpu_characteristics(struct gk20a *g) +{ + struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; + + int err; + + err = gk20a_init_gpu_characteristics(g); + if (err) + return err; + + gpu->flags |= + NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + + return 0; +} + + + +static const struct gpu_ops gv100_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gp10b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = gv11b_ce_get_num_pce, + }, + .fifo = { + .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, + .bind_channel = channel_gm20b_bind, + .unbind_channel = channel_gv11b_unbind, + .disable_channel = gk20a_fifo_disable_channel, + .enable_channel = gk20a_fifo_enable_channel, + .alloc_inst = gk20a_fifo_alloc_inst, + .free_inst = gk20a_fifo_free_inst, + .setup_ramfc = channel_gv11b_setup_ramfc, + .channel_set_priority = gk20a_fifo_set_priority, + .channel_set_timeslice = gk20a_fifo_set_timeslice, + .default_timeslice_us = gk20a_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = gv11b_fifo_preempt_channel, + .preempt_tsg = gv11b_fifo_preempt_tsg, + .update_runlist = gk20a_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = gk20a_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, + .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, + .force_reset_ch = gk20a_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = gk20a_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = gk20a_tsg_bind_channel, + .tsg_unbind_channel = gk20a_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, + .gr_ctx = { + .get_netlist_name = gr_gv100_get_netlist_name, + .is_fw_defined = gr_gv100_is_firmware_defined, + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, + .free_user_buffer = gk20a_ctxsw_dev_ring_free, + .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, + .init = gk20a_fecs_trace_init, + .deinit = gk20a_fecs_trace_deinit, + .enable = gk20a_fecs_trace_enable, + .disable = gk20a_fecs_trace_disable, + .is_enabled = gk20a_fecs_trace_is_enabled, + .reset = gk20a_fecs_trace_reset, + .flush = gp10b_fecs_trace_flush, + .poll = gk20a_fecs_trace_poll, + .bind_channel = gk20a_fecs_trace_bind_channel, + .unbind_channel = gk20a_fecs_trace_unbind_channel, + .max_entries = gk20a_gr_max_entries, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ + .pramin = { + .enter = gk20a_pramin_enter, + .exit = gk20a_pramin_exit, + .data032_r = pram_data032_r, + }, + .clk = { + .init_clk_support = gp106_init_clk_support, + .get_crystal_clk_hz = gp106_crystal_clk_hz, + .measure_freq = gp106_clk_measure_freq, + .suspend_clk_support = gp106_suspend_clk_support, + }, + .clk_arb = { + .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, + .get_arbiter_clk_range = gp106_get_arbiter_clk_range, + .get_arbiter_clk_default = gp106_get_arbiter_clk_default, + .get_current_pstate = nvgpu_clk_arb_get_current_pstate, + }, + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, + .debug = { + .show_dump = gk20a_debug_show_dump, + }, + .dbg_session_ops = { + .exec_reg_ops = exec_regops_gk20a, + .dbg_set_powergate = dbg_set_powergate, + .check_and_set_global_reservation = + nvgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + nvgpu_check_and_set_context_reservation, + .release_profiler_reservation = + nvgpu_release_profiler_reservation, + .perfbuffer_enable = gk20a_perfbuf_enable_locked, + .perfbuffer_disable = gk20a_perfbuf_disable_locked, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = gk20a_read_ptimer, + .bar1_bind = NULL, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = css_hw_enable_snapshot, + .disable_snapshot = css_hw_disable_snapshot, + .check_data_available = css_hw_check_data_available, + .set_handled_snapshots = css_hw_set_handled_snapshots, + .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, + .release_perfmon_ids = css_gr_release_perfmon_ids, + }, +#endif + .xve = { + .sw_init = xve_sw_init_gp106, + .get_speed = xve_get_speed_gp106, + .set_speed = xve_set_speed_gp106, + .available_speeds = xve_available_speeds_gp106, + .xve_readl = xve_xve_readl_gp106, + .xve_writel = xve_xve_writel_gp106, + .disable_aspm = xve_disable_aspm_gp106, + .reset_gpu = xve_reset_gpu_gp106, +#if defined(CONFIG_PCI_MSI) + .rearm_msi = xve_rearm_msi_gp106, +#endif + .enable_shadow_rom = xve_enable_shadow_rom_gp106, + .disable_shadow_rom = xve_disable_shadow_rom_gp106, + }, + .falcon = { + .falcon_hal_sw_init = gp106_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, + .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, + .get_litter_value = gv100_get_litter_value, + .bios_init = gm206_bios_init, +}; + +int gv100_init_hal(struct gk20a *g) +{ + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + + gops->ltc = gv100_ops.ltc; + gops->ce2 = gv100_ops.ce2; + gops->clock_gating = gv100_ops.clock_gating; + gops->fifo = gv100_ops.fifo; + gops->gr_ctx = gv100_ops.gr_ctx; + gops->fecs_trace = gv100_ops.fecs_trace; + gops->pramin = gv100_ops.pramin; + gops->therm = gv100_ops.therm; + gops->mc = gv100_ops.mc; + gops->debug = gv100_ops.debug; + gops->dbg_session_ops = gv100_ops.dbg_session_ops; + gops->bus = gv100_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = gv100_ops.css; +#endif + gops->xve = gv100_ops.xve; + gops->falcon = gv100_ops.falcon; + gops->priv_ring = gv100_ops.priv_ring; + + /* clocks */ + gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; + gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; + gops->clk.measure_freq = gv100_ops.clk.measure_freq; + gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + gv100_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gv100_ops.get_litter_value; + gops->bios_init = gv100_ops.bios_init; + + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + /* for now */ + __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + + g->bootstrap_owner = LSF_FALCON_ID_SEC2; + + gv11b_init_gr(g); + gv100_init_fb(gops); + gv100_init_mm(gops); + gp106_init_pmu_ops(g); + + g->name = "gv10x"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; + + return 0; +} diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h new file mode 100644 index 00000000..a7c74db0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h @@ -0,0 +1,21 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_HAL_GV11B_H +#define _NVGPU_HAL_GV11B_H +struct gk20a; + +int gv100_init_hal(struct gk20a *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c new file mode 100644 index 00000000..fbc5df79 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -0,0 +1,41 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gv11b/mm_gv11b.h" +#include "gv100/mm_gv100.h" + +#include + +static size_t gv100_mm_get_vidmem_size(struct gk20a *g) +{ + u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); + u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); + u32 scale = fb_mmu_local_memory_range_lower_scale_v(range); + u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range); + size_t bytes = ((size_t)mag << scale) * SZ_1M; + + if (ecc) + bytes = bytes / 16 * 15; + + return bytes; +} + +void gv100_init_mm(struct gpu_ops *gops) +{ + gv11b_init_mm(gops); + gops->mm.get_vidmem_size = gv100_mm_get_vidmem_size; + gops->mm.get_physical_addr_bits = NULL; +} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h new file mode 100644 index 00000000..ff1bc3df --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -0,0 +1,23 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MM_GV100_H +#define MM_GV100_H + +struct gpu_ops; + +void gv100_init_mm(struct gpu_ops *gops); + +#endif -- cgit v1.2.2 From 4bb0896912440d126ae47da350b448f37dabc63d Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 14:40:46 -0700 Subject: gpu: nvgpu: Reorg fb HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537748 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 9 +-------- drivers/gpu/nvgpu/gv100/fb_gv100.h | 4 ++-- drivers/gpu/nvgpu/gv100/hal_gv100.c | 28 ++++++++++++++++++++++++++-- 3 files changed, 29 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index a3785266..319ebad6 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -21,7 +21,6 @@ #include #include "gk20a/gk20a.h" -#include "gv11b/fb_gv11b.h" #include "gv100/fb_gv100.h" #include @@ -29,7 +28,7 @@ #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ -static void gv100_fb_reset(struct gk20a *g) +void gv100_fb_reset(struct gk20a *g) { u32 val; int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; @@ -50,9 +49,3 @@ static void gv100_fb_reset(struct gk20a *g) val &= ~fb_mmu_priv_level_mask_write_violation_m(); gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); } - -void gv100_init_fb(struct gpu_ops *gops) -{ - gv11b_init_fb(gops); - gops->fb.reset = gv100_fb_reset; -} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h index b234fa13..f3219177 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -16,7 +16,7 @@ #ifndef _NVGPU_GV100_FB #define _NVGPU_GV100_FB -struct gpu_ops; +struct gk20a; -void gv100_init_fb(struct gpu_ops *gops); +void gv100_fb_reset(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 337c607f..a2a131da 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -30,10 +30,14 @@ #include "gk20a/pramin_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" +#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/fb_gm20b.h" + +#include "gp10b/fb_gp10b.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" @@ -61,7 +65,7 @@ #include "gv100/gr_ctx_gv100.h" #include "gv100/mm_gv100.h" #include "gv11b/pmu_gv11b.h" -#include "gv100/fb_gv100.h" +#include "gv11b/fb_gv11b.h" #include "gv11b/fifo_gv11b.h" #include "gv11b/gv11b_gating_reglist.h" #include "gv11b/regops_gv11b.h" @@ -69,6 +73,7 @@ #include "gv100.h" #include "hal_gv100.h" +#include "gv100/fb_gv100.h" #include #include @@ -200,6 +205,23 @@ static const struct gpu_ops gv100_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .fb = { + .reset = gv100_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, + .set_debug_mode = gm20b_fb_set_debug_mode, + .tlb_invalidate = gk20a_fb_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, .fifo = { .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, .bind_channel = channel_gm20b_bind, @@ -424,10 +446,12 @@ int gv100_init_hal(struct gk20a *g) g->bootstrap_owner = LSF_FALCON_ID_SEC2; gv11b_init_gr(g); - gv100_init_fb(gops); gv100_init_mm(gops); gp106_init_pmu_ops(g); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->name = "gv10x"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 8ab6445df5b24c200ac4e346684119a85008e0e3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: Reorg mm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537754 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 33 +++++++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv100/mm_gv100.c | 10 +--------- drivers/gpu/nvgpu/gv100/mm_gv100.h | 4 ++-- 3 files changed, 34 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a2a131da..74bc48fb 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -31,11 +31,13 @@ #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/fb_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b/fb_gp10b.h" @@ -55,6 +57,7 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" @@ -63,7 +66,7 @@ #include "gv11b/gv11b.h" #include "gv11b/ce_gv11b.h" #include "gv100/gr_ctx_gv100.h" -#include "gv100/mm_gv100.h" +#include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" #include "gv11b/fb_gv11b.h" #include "gv11b/fifo_gv11b.h" @@ -74,6 +77,7 @@ #include "gv100.h" #include "hal_gv100.h" #include "gv100/fb_gv100.h" +#include "gv100/mm_gv100.h" #include #include @@ -310,6 +314,32 @@ static const struct gpu_ops gv100_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gv11b_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gv11b_gpu_phys_addr, + .get_physical_addr_bits = NULL, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .get_vidmem_size = gv100_mm_get_vidmem_size, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gv11b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, .pramin = { .enter = gk20a_pramin_enter, .exit = gk20a_pramin_exit, @@ -446,7 +476,6 @@ int gv100_init_hal(struct gk20a *g) g->bootstrap_owner = LSF_FALCON_ID_SEC2; gv11b_init_gr(g); - gv100_init_mm(gops); gp106_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c index fbc5df79..6952cb5e 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -14,12 +14,11 @@ */ #include "gk20a/gk20a.h" -#include "gv11b/mm_gv11b.h" #include "gv100/mm_gv100.h" #include -static size_t gv100_mm_get_vidmem_size(struct gk20a *g) +size_t gv100_mm_get_vidmem_size(struct gk20a *g) { u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); @@ -32,10 +31,3 @@ static size_t gv100_mm_get_vidmem_size(struct gk20a *g) return bytes; } - -void gv100_init_mm(struct gpu_ops *gops) -{ - gv11b_init_mm(gops); - gops->mm.get_vidmem_size = gv100_mm_get_vidmem_size; - gops->mm.get_physical_addr_bits = NULL; -} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h index ff1bc3df..eeab7d56 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.h +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -16,8 +16,8 @@ #ifndef MM_GV100_H #define MM_GV100_H -struct gpu_ops; +struct gk20a; -void gv100_init_mm(struct gpu_ops *gops); +size_t gv100_mm_get_vidmem_size(struct gk20a *g); #endif -- cgit v1.2.2 From cce0a55d2106865be14b3b39c083a0f55881f2a5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 1 Aug 2017 17:12:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg pmu HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3f8a763a7bebf201c2242eecde7ff998aad07d0a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 51 +++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 74bc48fb..bd13ec08 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -32,19 +32,23 @@ #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" #include "gk20a/mm_gk20a.h" +#include "gk20a/pmu_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/mm_gm20b.h" +#include "gm20b/pmu_gm20b.h" +#include "gm20b/acr_gm20b.h" #include "gp10b/fb_gp10b.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" #include "gp106/pmu_gp106.h" - +#include "gp106/acr_gp106.h" +#include "gp106/sec2_gp106.h" #include "gm206/bios_gm206.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" @@ -58,6 +62,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/pmu_gp10b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" @@ -87,6 +92,7 @@ #include #include #include +#include static int gv100_get_litter_value(struct gk20a *g, int value) { @@ -345,6 +351,45 @@ static const struct gpu_ops gv100_ops = { .exit = gk20a_pramin_exit, .data032_r = pram_data032_r, }, + .pmu = { + .init_wpr_region = gm20b_pmu_init_acr, + .load_lsfalcon_ucode = gp106_load_falcon_ucode, + .is_lazy_bootstrap = gp106_is_lazy_bootstrap, + .is_priv_load = gp106_is_priv_load, + .prepare_ucode = gp106_prepare_ucode_blob, + .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, + .get_wpr = gp106_wpr_info, + .alloc_blob_space = gp106_alloc_blob_space, + .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, + .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, + .falcon_wait_for_halt = sec2_wait_for_halt, + .falcon_clear_halt_interrupt_status = + sec2_clear_halt_interrupt_status, + .init_falcon_setup_hw = init_sec2_setup_hw1, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .is_pmu_supported = gp106_is_pmu_supported, + .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_is_lpwr_feature_supported = + gp106_pmu_is_lpwr_feature_supported, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_pg_param_post_init = nvgpu_lpwr_post_init, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_pg_init_param = gp106_pg_param_init, + .reset_engine = gp106_pmu_engine_reset, + .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, + }, .clk = { .init_clk_support = gp106_init_clk_support, .get_crystal_clk_hz = gp106_crystal_clk_hz, @@ -444,6 +489,7 @@ int gv100_init_hal(struct gk20a *g) gops->fecs_trace = gv100_ops.fecs_trace; gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; + gops->pmu = gv100_ops.pmu; gops->mc = gv100_ops.mc; gops->debug = gv100_ops.debug; gops->dbg_session_ops = gv100_ops.dbg_session_ops; @@ -470,13 +516,14 @@ int gv100_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); /* for now */ __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; gv11b_init_gr(g); - gp106_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); -- cgit v1.2.2 From 2370fce04396b4bb66b679a54112731a0dbd7018 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 18 Aug 2017 10:35:34 -0700 Subject: gpu: nvpgu: gv100: Enable gv100 fb and mm ops Assign fb and mm ops for gv100. Change-Id: I031031935cdb1fa33fd9f06af2f2229480740bc5 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1541339 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index bd13ec08..e3c2d1cb 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -483,9 +483,11 @@ int gv100_init_hal(struct gk20a *g) gops->ltc = gv100_ops.ltc; gops->ce2 = gv100_ops.ce2; + gops->fb = gv100_ops.fb; gops->clock_gating = gv100_ops.clock_gating; gops->fifo = gv100_ops.fifo; gops->gr_ctx = gv100_ops.gr_ctx; + gops->mm = gv100_ops.mm; gops->fecs_trace = gv100_ops.fecs_trace; gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; -- cgit v1.2.2 From 866165749a0b7b2e6b219bb26bffd69d790d97c5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 17 Aug 2017 16:10:42 -0700 Subject: gpu: nvgpu: Reorg gr HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1542988 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 149 +++++++++++++++++++++++++++++++++++- 1 file changed, 147 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e3c2d1cb..4f21e433 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -33,6 +33,7 @@ #include "gk20a/fb_gk20a.h" #include "gk20a/mm_gk20a.h" #include "gk20a/pmu_gk20a.h" +#include "gk20a/gr_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -43,6 +44,7 @@ #include "gm20b/acr_gm20b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/gr_gp10b.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" @@ -215,6 +217,150 @@ static const struct gpu_ops gv100_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .gr = { + .init_gpc_mmu = gr_gv11b_init_gpc_mmu, + .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, + .cb_size_default = gr_gv11b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gv11b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, + .commit_global_pagepool = gr_gp10b_commit_global_pagepool, + .handle_sw_method = gr_gv11b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gv11b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, + .is_valid_class = gr_gv11b_is_valid_class, + .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, + .is_valid_compute_class = gr_gv11b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = gr_gv11b_init_fs_state, + .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, + .free_channel_ctx = gk20a_free_channel_ctx, + .alloc_obj_ctx = gk20a_alloc_obj_ctx, + .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, + .get_zcull_info = gr_gk20a_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = gr_gv11b_detect_sm_arch, + .add_zbc_color = gr_gp10b_add_zbc_color, + .add_zbc_depth = gr_gp10b_add_zbc_depth, + .zbc_set_table = gk20a_gr_zbc_set_table, + .zbc_query_table = gr_gk20a_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gv11b_pagepool_default_size, + .init_ctx_state = gr_gp10b_init_ctx_state, + .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, + .free_gr_ctx = gr_gp10b_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode, + .dump_gr_regs = gr_gv11b_dump_gr_status_regs, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, + .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, + .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, + .get_max_fbps_count = gr_gm20b_get_max_fbps_count, + .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, + .wait_empty = gr_gv11b_wait_empty, + .init_cyclestats = gr_gv11b_init_cyclestats, + .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gv11b_gr_bpt_reg_info, + .get_access_map = gr_gv11b_get_access_map, + .handle_fecs_error = gr_gv11b_handle_fecs_error, + .handle_sm_exception = gr_gk20a_handle_sm_exception, + .handle_tex_exception = gr_gv11b_handle_tex_exception, + .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, + .enable_exceptions = gr_gv11b_enable_exceptions, + .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .record_sm_error_state = gv11b_gr_record_sm_error_state, + .update_sm_error_state = gv11b_gr_update_sm_error_state, + .clear_sm_error_state = gm20b_gr_clear_sm_error_state, + .suspend_contexts = gr_gp10b_suspend_contexts, + .resume_contexts = gr_gk20a_resume_contexts, + .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, + .fuse_override = gp10b_gr_fuse_override, + .init_sm_id_table = gr_gv11b_init_sm_id_table, + .load_smid_config = gr_gv11b_load_smid_config, + .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gv11b_setup_rop_mapping, + .program_zcull_mapping = gr_gv11b_program_zcull_mapping, + .commit_global_timeslice = gr_gv11b_commit_global_timeslice, + .commit_inst = gr_gv11b_commit_inst, + .write_zcull_ptr = gr_gv11b_write_zcull_ptr, + .write_pm_ptr = gr_gv11b_write_pm_ptr, + .init_elcg_mode = gr_gv11b_init_elcg_mode, + .load_tpc_mask = gr_gv11b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gv11b_gr_sm_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gv11b_gr_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, + .sm_debugger_attached = gv11b_gr_sm_debugger_attached, + .suspend_single_sm = gv11b_gr_suspend_single_sm, + .suspend_all_sms = gv11b_gr_suspend_all_sms, + .resume_single_sm = gv11b_gr_resume_single_sm, + .resume_all_sms = gv11b_gr_resume_all_sms, + .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gv11b_gr_lock_down_sm, + .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, + .clear_sm_hww = gv11b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .set_boosted_ctx = gr_gp10b_set_boosted_ctx, + .set_preemption_mode = gr_gp10b_set_preemption_mode, + .set_czf_bypass = NULL, + .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, + .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, + .init_preemption_state = NULL, + .update_boosted_ctx = gr_gp10b_update_boosted_ctx, + .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, + .create_gr_sysfs = gr_gv11b_create_sysfs, + .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, + .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, + .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, + .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, + .zbc_s_query_table = gr_gv11b_zbc_s_query_table, + .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, + .restore_context_header = gv11b_restore_context_header, + .handle_gpc_gpcmmu_exception = + gr_gv11b_handle_gpc_gpcmmu_exception, + .add_zbc_type_s = gr_gv11b_add_zbc_type_s, + .get_egpc_base = gv11b_gr_get_egpc_base, + .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, + .handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception, + .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, + .access_smpc_reg = gv11b_gr_access_smpc_reg, + .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, + .add_zbc_s = gr_gv11b_add_zbc_stencil, + .handle_gcc_exception = gr_gv11b_handle_gcc_exception, + .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, + .handle_tpc_sm_ecc_exception = + gr_gv11b_handle_tpc_sm_ecc_exception, + .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + }, .fb = { .reset = gv100_fb_reset, .init_hw = gk20a_fb_init_hw, @@ -483,6 +629,7 @@ int gv100_init_hal(struct gk20a *g) gops->ltc = gv100_ops.ltc; gops->ce2 = gv100_ops.ce2; + gops->gr = gv100_ops.gr; gops->fb = gv100_ops.fb; gops->clock_gating = gv100_ops.clock_gating; gops->fifo = gv100_ops.fifo; @@ -525,8 +672,6 @@ int gv100_init_hal(struct gk20a *g) g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; - gv11b_init_gr(g); - gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); -- cgit v1.2.2 From f98e3c8348d20b6542c4d27921cb9f9822aaa17a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 6 Sep 2017 14:45:30 -0700 Subject: gpu: nvgpu: gv100: Don't assign XVE sw_init XVE sw_init HAL is removed due to moving XVE debugfs code to Linux module. Remove the assignment of the HAL. Change-Id: I90beada58f87c78dc752011ea3ec2a5473f0acc1 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1553913 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4f21e433..cd121455 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -597,7 +597,6 @@ static const struct gpu_ops gv100_ops = { }, #endif .xve = { - .sw_init = xve_sw_init_gp106, .get_speed = xve_get_speed_gp106, .set_speed = xve_set_speed_gp106, .available_speeds = xve_available_speeds_gp106, -- cgit v1.2.2 From 52f50addc6cedf57fc3d8ff06314921499fb59e3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 13 Sep 2017 17:35:03 +0530 Subject: gpu: nvgpu: add TSG enable/disable operations Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cd121455..cc20fa43 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -397,6 +397,8 @@ static const struct gpu_ops gv100_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = gv11b_fifo_preempt_channel, .preempt_tsg = gv11b_fifo_preempt_tsg, + .enable_tsg = gv11b_fifo_enable_tsg, + .disable_tsg = gk20a_disable_tsg, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, -- cgit v1.2.2 From f720b309f1ea87a301bcb216983396f3d9c55abc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 14 Sep 2017 05:48:07 -0700 Subject: gpu: nvgpu: add tsg_verify_status_faulted operation Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cc20fa43..9a2807a2 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -399,6 +399,8 @@ static const struct gpu_ops gv100_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, -- cgit v1.2.2 From 0a0da216db25e293c68b5c9c6fa88e559368dce2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 19 Sep 2017 12:12:49 -0700 Subject: gpu: nvgpu: Use VBIOS HAL from gp106 instead of gm206 Use VBIOS HAL from gp106 instead of gm206. JIRA NVGPU-218 Change-Id: I835a1ce39818221f976ed5eca2bf3032317760b0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1563741 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9a2807a2..23ada798 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -51,7 +51,7 @@ #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" #include "gp106/sec2_gp106.h" -#include "gm206/bios_gm206.h" +#include "gp106/bios_gp106.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" #include "gp106/clk_gp106.h" @@ -622,7 +622,7 @@ static const struct gpu_ops gv100_ops = { }, .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, .get_litter_value = gv100_get_litter_value, - .bios_init = gm206_bios_init, + .bios_init = gp106_bios_init, }; int gv100_init_hal(struct gk20a *g) -- cgit v1.2.2 From a24382d09788ffc8f8688a473a38d37df589b131 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Sep 2017 22:34:54 +0530 Subject: gpu: nvgpu: Add support for WPR info read from FB update .read_wpr_info HAL of gv11b & gv100 to point to gm20b_fb_read_wpr_info() JIRA NVGPU-128 Change-Id: I5ece4c72dbe0f9e7827888e2a15d8b7dda6fcb42 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1564684 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 23ada798..3dfe9e74 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -373,6 +373,7 @@ static const struct gpu_ops gv100_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .vpr_info_fetch = gm20b_fb_vpr_info_fetch, .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, -- cgit v1.2.2 From 4d5216922b288a70f7434ac8f7c6c8274cc1462b Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 21 Sep 2017 09:09:24 -0700 Subject: gpu: nvgpu: fix coverity issues in GV100 HAL Fix value overwrite in switch statement on GV100 proj assignments bug 200291879 Change-Id: Id25f811f820a05b3d50cc9070369fe52f65a6bf3 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1565538 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 3dfe9e74..8cf8e245 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -138,6 +138,7 @@ static int gv100_get_litter_value(struct gk20a *g, int value) break; case GPU_LIT_PPC_IN_GPC_BASE: ret = proj_ppc_in_gpc_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 23 ++++++++++++++++------- drivers/gpu/nvgpu/gv100/fb_gv100.h | 23 ++++++++++++++++------- drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 23 ++++++++++++++++------- drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | 24 +++++++++++++++--------- drivers/gpu/nvgpu/gv100/gv100.h | 24 +++++++++++++++--------- drivers/gpu/nvgpu/gv100/hal_gv100.c | 23 ++++++++++++++++------- drivers/gpu/nvgpu/gv100/hal_gv100.h | 23 ++++++++++++++++------- drivers/gpu/nvgpu/gv100/mm_gv100.c | 23 ++++++++++++++++------- drivers/gpu/nvgpu/gv100/mm_gv100.h | 23 ++++++++++++++++------- 9 files changed, 142 insertions(+), 67 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index 319ebad6..bcb6d740 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h index f3219177..d5a36661 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_GV100_FB diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c index 2e605cce..9f13abce 100644 --- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h index 122e750f..2302d988 100644 --- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __GR_CTX_GV100_H__ #define __GR_CTX_GV100_H__ diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h index eeea64a4..7cc1f77b 100644 --- a/drivers/gpu/nvgpu/gv100/gv100.h +++ b/drivers/gpu/nvgpu/gv100/gv100.h @@ -3,17 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef GV100_H diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 8cf8e245..caa43a95 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h index a7c74db0..7dcf1d77 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.h +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_HAL_GV11B_H diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c index 6952cb5e..93688206 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h index eeab7d56..eba724f9 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.h +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef MM_GV100_H -- cgit v1.2.2 From 058485d28538b033636180c11592a9088878c807 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 27 Sep 2017 14:15:02 -0700 Subject: gpu: nvgpu: gv100: disable ctxsw trace ctxsw_trace need modifications with subcontext. Disable it for time-being. Change-Id: I0f0e3d0653e159dca09c40c8d0b4c46643cd0496 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1569629 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Martinez Nieto Tested-by: David Martinez Nieto Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index caa43a95..c9b9a1ca 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -465,20 +465,20 @@ static const struct gpu_ops gv100_ops = { }, #ifdef CONFIG_GK20A_CTXSW_TRACE .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = gk20a_fecs_trace_init, - .deinit = gk20a_fecs_trace_deinit, - .enable = gk20a_fecs_trace_enable, - .disable = gk20a_fecs_trace_disable, - .is_enabled = gk20a_fecs_trace_is_enabled, - .reset = gk20a_fecs_trace_reset, - .flush = gp10b_fecs_trace_flush, - .poll = gk20a_fecs_trace_poll, - .bind_channel = gk20a_fecs_trace_bind_channel, - .unbind_channel = gk20a_fecs_trace_unbind_channel, - .max_entries = gk20a_gr_max_entries, + .alloc_user_buffer = NULL, + .free_user_buffer = NULL, + .mmap_user_buffer = NULL, + .init = NULL, + .deinit = NULL, + .enable = NULL, + .disable = NULL, + .is_enabled = NULL, + .reset = NULL, + .flush = NULL, + .poll = NULL, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = NULL, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { -- cgit v1.2.2 From dc5edb1417390b583b5ff2406e554ce0770e02ae Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 16 Aug 2017 16:13:18 -0700 Subject: gpu: nvgpu: rename ops.mm.get_physical_addr_bits T19x/gv100 version of same patch in kernel/nvgpu. Change-Id: I7174864cf1e072af61609c0843da16fcafe54c02 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1566750 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index c9b9a1ca..72864c5f 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -494,7 +494,6 @@ static const struct gpu_ops gv100_ops = { .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gv11b_gpu_phys_addr, - .get_physical_addr_bits = NULL, .get_mmu_levels = gp10b_mm_get_mmu_levels, .get_vidmem_size = gv100_mm_get_vidmem_size, .init_pdb = gp10b_mm_init_pdb, -- cgit v1.2.2 From 19d602da31f81d9dc89a42b2bc84ce14a300773b Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 3 Oct 2017 14:01:51 +0530 Subject: gpu: nvgpu: verify channel status while closing per-platform We right now call gk20a_fifo_tsg_unbind_channel_verify_status() to verify channel status while unbinding a channel from TSG while closing Add support to do this verification per-platform and keep this disabled for vgpu platforms Bug 200327095 Change-Id: I6e2a6a09c784d24ac49477d5450b7d4b671878e3 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1572369 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 72864c5f..028c9d84 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -410,6 +410,7 @@ static const struct gpu_ops gv100_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, -- cgit v1.2.2 From f518304e0d8102216c7c0022cd4b66fcd844264c Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: fix GV100 hal definitions These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/bios_gv100.c | 108 +++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/bios_gv100.h | 31 ++++++++++ drivers/gpu/nvgpu/gv100/fifo_gv100.c | 32 +++++++++++ drivers/gpu/nvgpu/gv100/fifo_gv100.h | 32 +++++++++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 22 +++++-- 5 files changed, 219 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/bios_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/bios_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/fifo_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/fifo_gv100.h (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.c b/drivers/gpu/nvgpu/gv100/bios_gv100.c new file mode 100644 index 00000000..9ca05a11 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gp106/bios_gp106.h" +#include "bios_gv100.h" + +#include +#include + +#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ +#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ + +#define SCRATCH_PREOS_PROGRESS 6 +#define PREOS_PROGRESS_MASK(r) ((r >> 12) & 0xf) +#define PREOS_PROGRESS_NOT_STARTED 0 +#define PREOS_PROGRESS_STARTED 1 +#define PREOS_PROGRESS_EXIT 2 +#define PREOS_PROGRESS_EXIT_SECUREMODE 3 +#define PREOS_PROGRESS_ABORTED 6 + +#define SCRATCH_PMU_EXIT_AND_HALT 1 +#define PMU_EXIT_AND_HALT_SET(r, v) ((r & ~0x200UL) | v) +#define PMU_EXIT_AND_HALT_YES (0x1UL << 9) + +#define SCRATCH_PRE_OS_RELOAD 1 +#define PRE_OS_RELOAD_SET(r, v) ((r & ~0x100UL) | v) +#define PRE_OS_RELOAD_YES (0x1UL << 8) + + +void gv100_bios_preos_reload_check(struct gk20a *g) +{ + u32 progress = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); + + if (PREOS_PROGRESS_MASK(progress) != PREOS_PROGRESS_NOT_STARTED) { + u32 reload = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD)); + + gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD), + PRE_OS_RELOAD_SET(reload, PRE_OS_RELOAD_YES)); + } +} + +int gv100_bios_preos_wait_for_halt(struct gk20a *g) +{ + int err = -EINVAL; + u32 progress; + u32 tmp; + int preos_completed; + struct nvgpu_timeout timeout; + + nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); + + /* Check the progress */ + progress = gk20a_readl(g, bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); + + if (PREOS_PROGRESS_MASK(progress) == PREOS_PROGRESS_STARTED) { + err = 0; + + /* Complete the handshake */ + tmp = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT)); + + gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT), + PMU_EXIT_AND_HALT_SET(tmp, PMU_EXIT_AND_HALT_YES)); + + nvgpu_timeout_init(g, &timeout, + PMU_BOOT_TIMEOUT_MAX / + PMU_BOOT_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); + + do { + progress = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); + preos_completed = pwr_falcon_cpuctl_halt_intr_v( + gk20a_readl(g, pwr_falcon_cpuctl_r())) && + (PREOS_PROGRESS_MASK(progress) == + PREOS_PROGRESS_EXIT); + nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); + } while (!preos_completed && !nvgpu_timeout_expired(&timeout)); + } + + return err; +} diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.h b/drivers/gpu/nvgpu/gv100/bios_gv100.h new file mode 100644 index 00000000..c6433f57 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_BIOS_GV100_H +#define NVGPU_BIOS_GV100_H + +struct gk20a; + +void gv100_bios_preos_reload_check(struct gk20a *g); +int gv100_bios_preos_wait_for_halt(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c new file mode 100644 index 00000000..e19301e6 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c @@ -0,0 +1,32 @@ +/* + * GV100 fifo + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "fifo_gv100.h" + +#include + +u32 gv100_fifo_get_num_fifos(struct gk20a *g) +{ + return ccsr_channel__size_1_v(); +} diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h new file mode 100644 index 00000000..3ffb417c --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h @@ -0,0 +1,32 @@ +/* + * GV100 Fifo + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef FIFO_GV100_H +#define FIFO_GV100_H + +#include +struct gk20a; + +u32 gv100_fifo_get_num_fifos(struct gk20a *g); +#endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 028c9d84..7f7ab785 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -61,6 +61,7 @@ #include "gp106/acr_gp106.h" #include "gp106/sec2_gp106.h" #include "gp106/bios_gp106.h" +#include "gv100/bios_gv100.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" #include "gp106/clk_gp106.h" @@ -85,6 +86,10 @@ #include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" #include "gv11b/fb_gv11b.h" +#include "gv100/mm_gv100.h" +#include "gv11b/pmu_gv11b.h" +#include "gv100/fb_gv100.h" +#include "gv100/fifo_gv100.h" #include "gv11b/fifo_gv11b.h" #include "gv11b/gv11b_gating_reglist.h" #include "gv11b/regops_gv11b.h" @@ -208,6 +213,11 @@ int gv100_init_gpu_characteristics(struct gk20a *g) static const struct gpu_ops gv100_ops = { + .bios = { + .init = gp106_bios_init, + .preos_wait_for_halt = gv100_bios_preos_wait_for_halt, + .preos_reload_check = gv100_bios_preos_reload_check, + }, .ltc = { .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, @@ -218,7 +228,7 @@ static const struct gpu_ops gv100_ops = { .init_comptags = gp10b_ltc_init_comptags, .cbc_ctrl = gm20b_ltc_cbc_ctrl, .isr = gv11b_ltc_isr, - .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .cbc_fix_config = NULL, .flush = gm20b_flush_ltc, .set_enabled = gp10b_ltc_set_enabled, }, @@ -374,8 +384,7 @@ static const struct gpu_ops gv100_ops = { .fb = { .reset = gv100_fb_reset, .init_hw = gk20a_fb_init_hw, - .init_fs_state = gv11b_fb_init_fs_state, - .init_cbc = gv11b_fb_init_cbc, + .init_fs_state = NULL, .set_mmu_page_size = gm20b_fb_set_mmu_page_size, .set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line, @@ -417,7 +426,7 @@ static const struct gpu_ops gv100_ops = { .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, .wait_engine_idle = gk20a_fifo_wait_engine_idle, - .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_num_fifos = gv100_fifo_get_num_fifos, .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, @@ -633,7 +642,6 @@ static const struct gpu_ops gv100_ops = { }, .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, .get_litter_value = gv100_get_litter_value, - .bios_init = gp106_bios_init, }; int gv100_init_hal(struct gk20a *g) @@ -641,6 +649,7 @@ int gv100_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + gops->bios = gv100_ops.bios; gops->ltc = gv100_ops.ltc; gops->ce2 = gv100_ops.ce2; gops->gr = gv100_ops.gr; @@ -674,7 +683,6 @@ int gv100_init_hal(struct gk20a *g) gops->chip_init_gpu_characteristics = gv100_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv100_ops.get_litter_value; - gops->bios_init = gv100_ops.bios_init; __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); @@ -689,6 +697,8 @@ int gv100_init_hal(struct gk20a *g) gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); + g->bootstrap_owner = LSF_FALCON_ID_SEC2; + g->name = "gv10x"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From e78cd6c42aec3ae18f12420fd8eb4cb58d09da2d Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 12 Oct 2017 11:35:32 -0700 Subject: gpu: nvgpu: add missing hal defines Due to lack of GVS coverage some defines were left out in GV100, this change adds them back JIRA: NVGPUGV100-9 Change-Id: I2f5778529dcad535bb56c33c38c097415dbf11e5 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1577998 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7f7ab785..7457c185 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -91,6 +91,8 @@ #include "gv100/fb_gv100.h" #include "gv100/fifo_gv100.h" #include "gv11b/fifo_gv11b.h" +#include "gv11b/regops_gv11b.h" + #include "gv11b/gv11b_gating_reglist.h" #include "gv11b/regops_gv11b.h" #include "gv11b/subctx_gv11b.h" @@ -100,6 +102,7 @@ #include "gv100/fb_gv100.h" #include "gv100/mm_gv100.h" +#include #include #include @@ -156,6 +159,9 @@ static int gv100_get_litter_value(struct gk20a *g, int value) case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; + case GPU_LIT_PPC_IN_GPC_SHARED_BASE: + ret = proj_ppc_in_gpc_shared_base_v(); + break; case GPU_LIT_ROP_BASE: ret = proj_rop_base_v(); break; @@ -180,13 +186,30 @@ static int gv100_get_litter_value(struct gk20a *g, int value) case GPU_LIT_NUM_FBPAS: ret = proj_scal_litter_num_fbpas_v(); break; + case GPU_LIT_FBPA_SHARED_BASE: + ret = proj_fbpa_shared_base_v(); + break; + case GPU_LIT_FBPA_BASE: + ret = proj_fbpa_base_v(); + break; case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; - + case GPU_LIT_SMPC_PRI_BASE: + ret = proj_smpc_base_v(); + break; + case GPU_LIT_SMPC_PRI_SHARED_BASE: + ret = proj_smpc_shared_base_v(); + break; + case GPU_LIT_SMPC_PRI_UNIQUE_BASE: + ret = proj_smpc_unique_base_v(); + break; + case GPU_LIT_SMPC_PRI_STRIDE: + ret = proj_smpc_stride_v(); + break; default: break; } @@ -553,12 +576,10 @@ static const struct gpu_ops gv100_ops = { .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, .pmu_pg_init_param = gp106_pg_param_init, .reset_engine = gp106_pmu_engine_reset, - .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, .write_dmatrfbase = gp10b_write_dmatrfbase, .pmu_mutex_size = pwr_pmu_mutex__size_1_v, .is_engine_in_reset = gp106_pmu_is_engine_in_reset, .pmu_get_queue_tail = pwr_pmu_queue_tail_r, - .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, }, .clk = { .init_clk_support = gp106_init_clk_support, @@ -572,6 +593,9 @@ static const struct gpu_ops gv100_ops = { .get_arbiter_clk_default = gp106_get_arbiter_clk_default, .get_current_pstate = nvgpu_clk_arb_get_current_pstate, }, + .regops = { + .apply_smpc_war = gv11b_apply_smpc_war, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -601,13 +625,14 @@ static const struct gpu_ops gv100_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = gk20a_perfbuf_enable_locked, - .perfbuffer_disable = gk20a_perfbuf_disable_locked, + .perfbuffer_enable = NULL, + .perfbuffer_disable = NULL, }, .bus = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .read_ptimer = gk20a_read_ptimer, + .get_timestamps_zipper = nvgpu_get_timestamps_zipper, .bar1_bind = NULL, }, #if defined(CONFIG_GK20A_CYCLE_STATS) @@ -662,6 +687,7 @@ int gv100_init_hal(struct gk20a *g) gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; gops->pmu = gv100_ops.pmu; + gops->regops = gv100_ops.regops; gops->mc = gv100_ops.mc; gops->debug = gv100_ops.debug; gops->dbg_session_ops = gv100_ops.dbg_session_ops; -- cgit v1.2.2 From 201ccbfa8503daee9562a22f50a5b626fe4cc6a1 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 16 Oct 2017 12:14:29 -0700 Subject: gpu: nvgpu: gv11b: update dbg ops Updated following hal functions for gv11b and reused them for gv100: perfbuffer_enable perfbuffer_disable These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target to sys_ncoh_f(). Bug 200327596 Change-Id: Ia672ac561917c8ed36caea9cc7e74b7fc7ce8188 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1571074 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7457c185..2ece7be8 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -76,6 +76,7 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gv11b/dbg_gpu_gv11b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" #include "gv11b/mc_gv11b.h" @@ -625,8 +626,8 @@ static const struct gpu_ops gv100_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = NULL, - .perfbuffer_disable = NULL, + .perfbuffer_enable = gv11b_perfbuf_enable_locked, + .perfbuffer_disable = gv11b_perfbuf_disable_locked, }, .bus = { .init_hw = gk20a_bus_init_hw, -- cgit v1.2.2 From 62e133029d5a89e07e3ba5e96475c0960c0bc3dd Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 16 Oct 2017 12:38:46 -0700 Subject: gpu: nvgpu: Refactoring nvgpu_vm functions Change required for equivalent change on nvgpu. This is required since a few HALs were added that must be populated for all chips. This patch adds those HAL definitions for gv11b, gv100, and the vgpu. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I65374764350a5cacce8624b15d98947fada35a4a Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1579865 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 2ece7be8..9d033d6d 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -535,6 +535,8 @@ static const struct gpu_ops gv100_ops = { .is_bar1_supported = gv11b_mm_is_bar1_supported, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .get_kind_invalid = gm20b_get_kind_invalid, + .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gb10b_init_bar2_vm, .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, -- cgit v1.2.2 From 387ecf8a6360f463a129ab569aaef921fe0a2b0e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 18 Oct 2017 11:40:46 -0700 Subject: gpu: nvgpu: gv1xx: Remove HAL for restore_context_header gr restore_context_header is not required any more after enabling per context va mode for subcontext. Cleaning-up unused function pointers from gv100 and gv11b HAL. Change-Id: I65cc7d12d3c96726d323defd99726c3e259e7e63 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1581432 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9d033d6d..f20d2dcf 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -387,7 +387,6 @@ static const struct gpu_ops gv100_ops = { .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, .zbc_s_query_table = gr_gv11b_zbc_s_query_table, .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, - .restore_context_header = gv11b_restore_context_header, .handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception, .add_zbc_type_s = gr_gv11b_add_zbc_type_s, -- cgit v1.2.2 From ed8ac6e005d95e051bd03a182bbe0aa09a3c2266 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 16 Oct 2017 12:24:59 -0700 Subject: gpu: nvgpu: fix smid generation of perf tables SMID tables were generated according with the local tpc and the pagepool and cb buffers from a different chip and did not take performance in consideration, which made compute kernels hang with CTAs on the fly. This change ensures we are using the right sizes and adds proper enumeration of smids. JIRA: NVGPUGV100-36 bug 2004378 Change-Id: Ic8f50c325d6d6720cca41d9740ae4f5f51e1100a Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1581664 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 289 ++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/gr_gv100.h | 36 +++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 10 +- 3 files changed, 330 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/gr_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/gr_gv100.h (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c new file mode 100644 index 00000000..4b2038ba --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -0,0 +1,289 @@ +/* + * GV100 GPU GR + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/gr_gk20a.h" + +#include "gv100/gr_gv100.h" +#include "gv11b/subctx_gv11b.h" + +#include +#include + +/* + * Estimate performance if the given logical TPC in the given logical GPC were + * removed. + */ +static int gr_gv100_scg_estimate_perf(struct gk20a *g, + unsigned long *gpc_tpc_mask, + u32 disable_gpc_id, u32 disable_tpc_id, + int *perf) +{ + struct gr_gk20a *gr = &g->gr; + int err = 0; + u32 scale_factor = 512UL; /* Use fx23.9 */ + u32 pix_scale = 1024*1024UL; /* Pix perf in [29:20] */ + u32 world_scale = 1024UL; /* World performance in [19:10] */ + u32 tpc_scale = 1; /* TPC balancing in [9:0] */ + u32 scg_num_pes = 0; + u32 min_scg_gpc_pix_perf = scale_factor; /* Init perf as maximum */ + u32 average_tpcs = 0; /* Average of # of TPCs per GPC */ + u32 deviation; /* absolute diff between TPC# and + * average_tpcs, averaged across GPCs + */ + u32 norm_tpc_deviation; /* deviation/max_tpc_per_gpc */ + u32 tpc_balance; + u32 scg_gpc_pix_perf; + u32 scg_world_perf; + u32 gpc_id; + u32 pes_id; + int diff; + bool is_tpc_removed_gpc = false; + bool is_tpc_removed_pes = false; + u32 max_tpc_gpc = 0; + u32 num_tpc_mask; + u32 *num_tpc_gpc = nvgpu_kzalloc(g, sizeof(u32) * + nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS)); + + if (!num_tpc_gpc) + return -ENOMEM; + + /* Calculate pix-perf-reduction-rate per GPC and find bottleneck TPC */ + for (gpc_id = 0; gpc_id < gr->gpc_count; gpc_id++) { + num_tpc_mask = gpc_tpc_mask[gpc_id]; + + if ((gpc_id == disable_gpc_id) && num_tpc_mask & + (0x1 << disable_tpc_id)) { + /* Safety check if a TPC is removed twice */ + if (is_tpc_removed_gpc) { + err = -EINVAL; + goto free_resources; + } + /* Remove logical TPC from set */ + num_tpc_mask &= ~(0x1 << disable_tpc_id); + is_tpc_removed_gpc = true; + } + + /* track balancing of tpcs across gpcs */ + num_tpc_gpc[gpc_id] = hweight32(num_tpc_mask); + average_tpcs += num_tpc_gpc[gpc_id]; + + /* save the maximum numer of gpcs */ + max_tpc_gpc = num_tpc_gpc[gpc_id] > max_tpc_gpc ? + num_tpc_gpc[gpc_id] : max_tpc_gpc; + + /* + * Calculate ratio between TPC count and post-FS and post-SCG + * + * ratio represents relative throughput of the GPC + */ + scg_gpc_pix_perf = scale_factor * num_tpc_gpc[gpc_id] / + gr->gpc_tpc_count[gpc_id]; + + if (min_scg_gpc_pix_perf > scg_gpc_pix_perf) + min_scg_gpc_pix_perf = scg_gpc_pix_perf; + + /* Calculate # of surviving PES */ + for (pes_id = 0; pes_id < gr->gpc_ppc_count[gpc_id]; pes_id++) { + /* Count the number of TPC on the set */ + num_tpc_mask = gr->pes_tpc_mask[pes_id][gpc_id] & + gpc_tpc_mask[gpc_id]; + + if ((gpc_id == disable_gpc_id) && (num_tpc_mask & + (0x1 << disable_tpc_id))) { + + if (is_tpc_removed_pes) { + err = -EINVAL; + goto free_resources; + } + num_tpc_mask &= ~(0x1 << disable_tpc_id); + is_tpc_removed_pes = true; + } + if (hweight32(num_tpc_mask)) + scg_num_pes++; + } + } + + if (!is_tpc_removed_gpc || !is_tpc_removed_pes) { + err = -EINVAL; + goto free_resources; + } + + if (max_tpc_gpc == 0) { + *perf = 0; + goto free_resources; + } + + /* Now calculate perf */ + scg_world_perf = (scale_factor * scg_num_pes) / gr->ppc_count; + deviation = 0; + average_tpcs = scale_factor * average_tpcs / gr->gpc_count; + for (gpc_id =0; gpc_id < gr->gpc_count; gpc_id++) { + diff = average_tpcs - scale_factor * num_tpc_gpc[gpc_id]; + if (diff < 0) + diff = -diff; + deviation += diff; + } + + deviation /= gr->gpc_count; + + norm_tpc_deviation = deviation / max_tpc_gpc; + + tpc_balance = scale_factor - norm_tpc_deviation; + + if ((tpc_balance > scale_factor) || + (scg_world_perf > scale_factor) || + (min_scg_gpc_pix_perf > scale_factor) || + (norm_tpc_deviation > scale_factor)) { + err = -EINVAL; + goto free_resources; + } + + *perf = (pix_scale * min_scg_gpc_pix_perf) + + (world_scale * scg_world_perf) + + (tpc_scale * tpc_balance); +free_resources: + nvgpu_kfree(g, num_tpc_gpc); + return err; +} + +void gr_gv100_bundle_cb_defaults(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + gr->bundle_cb_default_size = + gr_scc_bundle_cb_size_div_256b__prod_v(); + gr->min_gpm_fifo_depth = + gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(); + gr->bundle_cb_token_limit = + gr_pd_ab_dist_cfg2_token_limit_init_v(); +} + +void gr_gv100_cb_size_default(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + if (!gr->attrib_cb_default_size) + gr->attrib_cb_default_size = + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); + gr->alpha_cb_default_size = + gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); +} + +void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) +{ +} + +void gr_gv100_init_sm_id_table(struct gk20a *g) +{ + u32 gpc, tpc, sm, pes, gtpc; + u32 sm_id = 0; + u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + u32 num_sm = sm_per_tpc * g->gr.tpc_count; + int perf, maxperf; + int err; + unsigned long *gpc_tpc_mask; + u32 *tpc_table, *gpc_table; + + gpc_table = nvgpu_kzalloc(g, g->gr.tpc_count * sizeof(u32)); + tpc_table = nvgpu_kzalloc(g, g->gr.tpc_count * sizeof(u32)); + gpc_tpc_mask = nvgpu_kzalloc(g, sizeof(unsigned long) * + nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS)); + + if (!gpc_table || !tpc_table || !gpc_tpc_mask) { + nvgpu_err(g, "Error allocating memory for sm tables"); + goto exit_build_table; + } + + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) + for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++) + gpc_tpc_mask[gpc] |= g->gr.pes_tpc_mask[pes][gpc]; + + for (gtpc = 0; gtpc < g->gr.tpc_count; gtpc++) { + maxperf = -1; + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + for_each_set_bit(tpc, &gpc_tpc_mask[gpc], + g->gr.gpc_tpc_count[gpc]) { + perf = -1; + err = gr_gv100_scg_estimate_perf(g, + gpc_tpc_mask, gpc, tpc, &perf); + + if (err) { + nvgpu_err(g, + "Error while estimating perf"); + goto exit_build_table; + } + + if (perf >= maxperf) { + maxperf = perf; + gpc_table[gtpc] = gpc; + tpc_table[gtpc] = tpc; + } + } + } + gpc_tpc_mask[gpc_table[gtpc]] &= ~(0x1 << tpc_table[gtpc]); + } + + for (tpc = 0, sm_id = 0; sm_id < num_sm; tpc++, sm_id += sm_per_tpc) { + for (sm = 0; sm < sm_per_tpc; sm++) { + g->gr.sm_to_cluster[sm_id + sm].gpc_index = + gpc_table[tpc]; + g->gr.sm_to_cluster[sm_id + sm].tpc_index = + tpc_table[tpc]; + g->gr.sm_to_cluster[sm_id + sm].sm_index = sm; + g->gr.sm_to_cluster[sm_id + sm].global_tpc_index = tpc; + } + } + + g->gr.no_of_sm = num_sm; + nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); +exit_build_table: + nvgpu_kfree(g, gpc_table); + nvgpu_kfree(g, tpc_table); + nvgpu_kfree(g, gpc_tpc_mask); +} + +void gr_gv100_load_tpc_mask(struct gk20a *g) +{ + u64 pes_tpc_mask = 0x0ULL; + u32 gpc, pes; + u32 num_tpc_per_gpc = nvgpu_get_litter_value(g, + GPU_LIT_NUM_TPC_PER_GPC); + + /* gv100 has 6 GPC and 7 TPC/GPC */ + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + for (pes = 0; pes < g->gr.pe_count_per_gpc; pes++) { + pes_tpc_mask |= (u64) g->gr.pes_tpc_mask[pes][gpc] << + (num_tpc_per_gpc * gpc); + } + } + + nvgpu_log_info(g, "pes_tpc_mask: %016llx\n", pes_tpc_mask); + gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask)); + gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask)); +} diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h new file mode 100644 index 00000000..460b05ae --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -0,0 +1,36 @@ +/* + * GV100 GPU GR + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GR_GV100_H_ +#define _NVGPU_GR_GV100_H_ + +void gr_gv100_bundle_cb_defaults(struct gk20a *g); +void gr_gv100_cb_size_default(struct gk20a *g); +void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); +void gr_gv100_init_sm_id_table(struct gk20a *g); +void gr_gv100_program_sm_id_numbering(struct gk20a *g, + u32 gpc, u32 tpc, u32 smid); +int gr_gv100_load_smid_config(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f20d2dcf..cefaf1ae 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -78,7 +78,7 @@ #include "gv11b/dbg_gpu_gv11b.h" #include "gv11b/hal_gv11b.h" -#include "gv11b/gr_gv11b.h" +#include "gv100/gr_gv100.h" #include "gv11b/mc_gv11b.h" #include "gv11b/ltc_gv11b.h" #include "gv11b/gv11b.h" @@ -263,8 +263,8 @@ static const struct gpu_ops gv100_ops = { }, .gr = { .init_gpc_mmu = gr_gv11b_init_gpc_mmu, - .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, - .cb_size_default = gr_gv11b_cb_size_default, + .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, + .cb_size_default = gr_gv100_cb_size_default, .calc_global_ctx_buffer_size = gr_gv11b_calc_global_ctx_buffer_size, .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, @@ -285,7 +285,7 @@ static const struct gpu_ops gv100_ops = { .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, - .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, .free_channel_ctx = gk20a_free_channel_ctx, .alloc_obj_ctx = gk20a_alloc_obj_ctx, @@ -335,7 +335,7 @@ static const struct gpu_ops gv100_ops = { .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, .fuse_override = gp10b_gr_fuse_override, - .init_sm_id_table = gr_gv11b_init_sm_id_table, + .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, -- cgit v1.2.2 From cf70c925cd3d8e6c83feee04316b080d5f258afc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 22 Jun 2017 16:28:19 -0700 Subject: gpu: nvgpu: gv11b: update css ops Updated following hal functions for css gv11b and reused them for gv100: enable_snapshot disable_snapshot check_data_available These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target based on memory aperture used for hwpm inst_block. Bug 200327596 Change-Id: I500d17670e2f389d8d0e77884374bcc3504a41f8 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1507546 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cefaf1ae..2007eee0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -76,6 +76,7 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gv11b/css_gr_gv11b.h" #include "gv11b/dbg_gpu_gv11b.h" #include "gv11b/hal_gv11b.h" #include "gv100/gr_gv100.h" @@ -639,9 +640,9 @@ static const struct gpu_ops gv100_ops = { }, #if defined(CONFIG_GK20A_CYCLE_STATS) .css = { - .enable_snapshot = css_hw_enable_snapshot, - .disable_snapshot = css_hw_disable_snapshot, - .check_data_available = css_hw_check_data_available, + .enable_snapshot = gv11b_css_hw_enable_snapshot, + .disable_snapshot = gv11b_css_hw_disable_snapshot, + .check_data_available = gv11b_css_hw_check_data_available, .set_handled_snapshots = css_hw_set_handled_snapshots, .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, .release_perfmon_ids = css_gr_release_perfmon_ids, -- cgit v1.2.2 From 2904e3ac0081d4e898378f6ba667658c85547368 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 4 Oct 2017 19:41:04 +0530 Subject: gpu: nvgpu: gv100 memory unlock support - Added method to load mem unlock binary into nvdec falcon & execute to perform mem unlock if VPR enabled. - Updated .mem_unlock gv100 HAL to point method gv100_fb_memory_unlock(). - Updated .mem_unlock gv11b HAL to NULL. - Added vpr info hw registers - Added nvdec enable hw register Change-Id: Ia4bf820ae103baede679d300d1d390fd748c919a Signed-off-by: Mahantesh Kumbar (cherry picked from commit 2e176ad9d47316bf4d001692a2ae07e6c1fb1ccb) Reviewed-on: https://git-master.nvidia.com/r/1573101 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 124 ++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/fb_gv100.h | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 3 files changed, 126 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index bcb6d740..0a2939bf 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -28,14 +28,25 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include "gk20a/gk20a.h" #include "gv100/fb_gv100.h" +#include "gm20b/acr_gm20b.h" #include +#include +#include #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ +#define MEM_UNLOCK_TIMEOUT 3500 /* msec */ void gv100_fb_reset(struct gk20a *g) { @@ -58,3 +69,116 @@ void gv100_fb_reset(struct gk20a *g) val &= ~fb_mmu_priv_level_mask_write_violation_m(); gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); } + +int gv100_fb_memory_unlock(struct gk20a *g) +{ + struct nvgpu_firmware *mem_unlock_fw = NULL; + struct bin_hdr *hsbin_hdr = NULL; + struct acr_fw_header *fw_hdr = NULL; + u32 *mem_unlock_ucode = NULL; + u32 *mem_unlock_ucode_header = NULL; + u32 sec_imem_dest = 0; + u32 val = 0; + int err = 0; + + nvgpu_log_fn(g, " "); + + /* Check vpr enable status */ + val = gk20a_readl(g, fb_mmu_vpr_info_r()); + val &= ~fb_mmu_vpr_info_index_m(); + val |= fb_mmu_vpr_info_index_cya_lo_v(); + gk20a_writel(g, fb_mmu_vpr_info_r(), val); + val = gk20a_readl(g, fb_mmu_vpr_info_r()); + if (!(val & fb_mmu_vpr_info_cya_lo_in_use_m())) { + nvgpu_log_info(g, "mem unlock not required on this SKU, skipping"); + goto exit; + } + + /* get mem unlock ucode binary */ + mem_unlock_fw = nvgpu_request_firmware(g, "mem_unlock.bin", 0); + if (!mem_unlock_fw) { + nvgpu_err(g, "mem unlock ucode get fail"); + err = -ENOENT; + goto exit; + } + + /* Enable nvdec */ + g->ops.mc.enable(g, mc_enable_nvdec_enabled_f()); + + /* nvdec falcon reset */ + nvgpu_flcn_reset(&g->nvdec_flcn); + + hsbin_hdr = (struct bin_hdr *)mem_unlock_fw->data; + fw_hdr = (struct acr_fw_header *)(mem_unlock_fw->data + + hsbin_hdr->header_offset); + + mem_unlock_ucode_header = (u32 *)(mem_unlock_fw->data + + fw_hdr->hdr_offset); + mem_unlock_ucode = (u32 *)(mem_unlock_fw->data + + hsbin_hdr->data_offset); + + /* Patch Ucode singnatures */ + if (acr_ucode_patch_sig(g, mem_unlock_ucode, + (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset), + (u32 *)(mem_unlock_fw->data + fw_hdr->sig_dbg_offset), + (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc), + (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) { + nvgpu_err(g, "mem unlock patch signatures fail"); + err = -EPERM; + goto exit; + } + + /* Clear interrupts */ + nvgpu_flcn_set_irq(&g->nvdec_flcn, false, 0x0, 0x0); + + /* Copy Non Secure IMEM code */ + nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, 0, + (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[OS_CODE_OFFSET] >> 2], + mem_unlock_ucode_header[OS_CODE_SIZE], 0, false, + GET_IMEM_TAG(mem_unlock_ucode_header[OS_CODE_OFFSET])); + + /* Put secure code after non-secure block */ + sec_imem_dest = GET_NEXT_BLOCK(mem_unlock_ucode_header[OS_CODE_SIZE]); + + nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, sec_imem_dest, + (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[APP_0_CODE_OFFSET] >> 2], + mem_unlock_ucode_header[APP_0_CODE_SIZE], 0, true, + GET_IMEM_TAG(mem_unlock_ucode_header[APP_0_CODE_OFFSET])); + + /* load DMEM: ensure that signatures are patched */ + nvgpu_flcn_copy_to_dmem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2], + mem_unlock_ucode_header[OS_DATA_SIZE], 0); + + nvgpu_log_info(g, "nvdec sctl reg %x\n", + gk20a_readl(g, g->nvdec_flcn.flcn_base + + falcon_falcon_sctl_r())); + + /* set BOOTVEC to start of non-secure code */ + nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0); + + /* wait for complete & halt */ + nvgpu_flcn_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT); + + /* check mem unlock status */ + val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0); + if (val) { + nvgpu_err(g, "memory unlock failed, err %x", val); + err = -1; + goto exit; + } + + nvgpu_log_info(g, "nvdec sctl reg %x\n", + gk20a_readl(g, g->nvdec_flcn.flcn_base + + falcon_falcon_sctl_r())); + +exit: + if (mem_unlock_fw) + nvgpu_release_firmware(g, mem_unlock_fw); + + nvgpu_log_fn(g, "done, status - %d", err); + + return err; +} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h index d5a36661..b6db262a 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -28,4 +28,5 @@ struct gk20a; void gv100_fb_reset(struct gk20a *g); +int gv100_fb_memory_unlock(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 2007eee0..4e05f22b 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -421,6 +421,7 @@ static const struct gpu_ops gv100_ops = { .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, .hub_isr = gv11b_fb_hub_isr, + .mem_unlock = gv100_fb_memory_unlock, }, .fifo = { .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, -- cgit v1.2.2 From 6114553413297dbcae637bc50ef2ff2a6c0858d1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 19 Oct 2017 10:12:24 -0700 Subject: gpu: nvgpu: gv100: fix timeout handling GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fifo_gv100.c | 8 ++++++++ drivers/gpu/nvgpu/gv100/fifo_gv100.h | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 ++++-- drivers/gpu/nvgpu/gv100/mm_gv100.c | 13 +++++++++++++ drivers/gpu/nvgpu/gv100/mm_gv100.h | 1 + 5 files changed, 27 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c index e19301e6..79862f6b 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c @@ -26,7 +26,15 @@ #include +#define DEFAULT_FIFO_PREEMPT_TIMEOUT 0x3FFFFFUL + u32 gv100_fifo_get_num_fifos(struct gk20a *g) { return ccsr_channel__size_1_v(); } + +u32 gv100_fifo_get_preempt_timeout(struct gk20a *g) +{ + return DEFAULT_FIFO_PREEMPT_TIMEOUT; +} + diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h index 3ffb417c..af6ad030 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h @@ -29,4 +29,5 @@ struct gk20a; u32 gv100_fifo_get_num_fifos(struct gk20a *g); +u32 gv100_fifo_get_preempt_timeout(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4e05f22b..ff852168 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -424,6 +424,7 @@ static const struct gpu_ops gv100_ops = { .mem_unlock = gv100_fb_memory_unlock, }, .fifo = { + .get_preempt_timeout = gv100_fifo_get_preempt_timeout, .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, .bind_channel = channel_gm20b_bind, .unbind_channel = channel_gv11b_unbind, @@ -470,7 +471,7 @@ static const struct gpu_ops gv100_ops = { .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, .is_preempt_pending = gv11b_fifo_is_preempt_pending, .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, - .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, .handle_sched_error = gv11b_fifo_handle_sched_error, .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, @@ -523,7 +524,7 @@ static const struct gpu_ops gv100_ops = { .vm_bind_channel = gk20a_vm_bind_channel, .fb_flush = gk20a_mm_fb_flush, .l2_invalidate = gk20a_mm_l2_invalidate, - .l2_flush = gv11b_mm_l2_flush, + .l2_flush = gk20a_mm_l2_flush, .cbc_clean = gk20a_mm_cbc_clean, .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, @@ -542,6 +543,7 @@ static const struct gpu_ops gv100_ops = { .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + .get_flush_retries = gv100_mm_get_flush_retries, }, .pramin = { .enter = gk20a_pramin_enter, diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c index 93688206..1b46faae 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -40,3 +40,16 @@ size_t gv100_mm_get_vidmem_size(struct gk20a *g) return bytes; } + +u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op) +{ + switch (op) { + /* GV100 has a large FB so it needs larger timeouts */ + case NVGPU_FLUSH_FB: + return 2000; + case NVGPU_FLUSH_L2_FLUSH: + return 2000; + default: + return 200; /* Default retry timer */ + } +} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h index eba724f9..ea896503 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.h +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -28,5 +28,6 @@ struct gk20a; size_t gv100_mm_get_vidmem_size(struct gk20a *g); +u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op); #endif -- cgit v1.2.2 From f8c2b77e4f64fcb4adc889bfc0bd4b9ad368ecc6 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 20 Oct 2017 14:58:13 -0700 Subject: gpu: nvgpu: Add gv10x regops whitelist Add regops whitelists for GV100 JIRA: NVGPUGV100-36 Change-Id: Ifeb286e2e8df056ba9afdd32f457bacf1b4813fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582835 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 24 +- drivers/gpu/nvgpu/gv100/regops_gv100.c | 463 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/regops_gv100.h | 42 +++ 3 files changed, 527 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/regops_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/regops_gv100.h (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index ff852168..3a8dc4b1 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -96,7 +96,7 @@ #include "gv11b/regops_gv11b.h" #include "gv11b/gv11b_gating_reglist.h" -#include "gv11b/regops_gv11b.h" +#include "gv100/regops_gv100.h" #include "gv11b/subctx_gv11b.h" #include "gv100.h" @@ -600,7 +600,27 @@ static const struct gpu_ops gv100_ops = { .get_current_pstate = nvgpu_clk_arb_get_current_pstate, }, .regops = { - .apply_smpc_war = gv11b_apply_smpc_war, + .get_global_whitelist_ranges = + gv100_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gv100_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gv100_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gv100_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gv100_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gv100_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gv100_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gv100_get_qctl_whitelist, + .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gv100_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gv100_apply_smpc_war, }, .mc = { .intr_enable = mc_gv11b_intr_enable, diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c new file mode 100644 index 00000000..00f05418 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c @@ -0,0 +1,463 @@ +/* + * Tegra GV100 GPU Driver Register Ops + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/regops_gk20a.h" +#include "regops_gv100.h" + +static const struct regop_offset_range gv100_global_whitelist_ranges[] = { + { 0x000004f0, 1}, + { 0x00001a00, 3}, + { 0x00002800, 128}, + { 0x00009400, 1}, + { 0x00009410, 1}, + { 0x00009480, 1}, + { 0x00020200, 24}, + { 0x00021c00, 4}, + { 0x00021c14, 3}, + { 0x00021c24, 1}, + { 0x00021c2c, 69}, + { 0x00021d44, 1}, + { 0x00021d4c, 1}, + { 0x00021d54, 1}, + { 0x00021d5c, 1}, + { 0x00021d64, 2}, + { 0x00021d70, 16}, + { 0x00022430, 7}, + { 0x00022450, 1}, + { 0x0002245c, 2}, + { 0x00070000, 5}, + { 0x000884e0, 1}, + { 0x0008e00c, 1}, + { 0x00100c18, 3}, + { 0x00100c84, 1}, + { 0x00104038, 1}, + { 0x0010a0a8, 1}, + { 0x0010a4f0, 1}, + { 0x0010e490, 1}, + { 0x0013cc14, 1}, + { 0x00140028, 1}, + { 0x00140280, 1}, + { 0x001402a0, 1}, + { 0x00140350, 1}, + { 0x00140480, 1}, + { 0x001404a0, 1}, + { 0x00140550, 1}, + { 0x00142028, 1}, + { 0x00142280, 1}, + { 0x001422a0, 1}, + { 0x00142350, 1}, + { 0x00142480, 1}, + { 0x001424a0, 1}, + { 0x00142550, 1}, + { 0x0017e028, 1}, + { 0x0017e280, 1}, + { 0x0017e294, 1}, + { 0x0017e29c, 2}, + { 0x0017e2ac, 1}, + { 0x0017e350, 1}, + { 0x0017e39c, 1}, + { 0x0017e480, 1}, + { 0x0017e4a0, 1}, + { 0x0017e550, 1}, + { 0x00180040, 41}, + { 0x001800ec, 10}, + { 0x00180240, 41}, + { 0x001802ec, 10}, + { 0x00180440, 41}, + { 0x001804ec, 10}, + { 0x00180640, 41}, + { 0x001806ec, 10}, + { 0x00180840, 41}, + { 0x001808ec, 10}, + { 0x00180a40, 41}, + { 0x00180aec, 10}, + { 0x00180c40, 41}, + { 0x00180cec, 10}, + { 0x00180e40, 41}, + { 0x00180eec, 10}, + { 0x001a0040, 41}, + { 0x001a00ec, 10}, + { 0x001a0240, 41}, + { 0x001a02ec, 10}, + { 0x001a0440, 41}, + { 0x001a04ec, 10}, + { 0x001a0640, 41}, + { 0x001a06ec, 10}, + { 0x001a0840, 41}, + { 0x001a08ec, 10}, + { 0x001a0a40, 41}, + { 0x001a0aec, 10}, + { 0x001a0c40, 41}, + { 0x001a0cec, 10}, + { 0x001a0e40, 41}, + { 0x001a0eec, 10}, + { 0x001b0040, 41}, + { 0x001b00ec, 10}, + { 0x001b0240, 41}, + { 0x001b02ec, 10}, + { 0x001b0440, 41}, + { 0x001b04ec, 10}, + { 0x001b0640, 41}, + { 0x001b06ec, 10}, + { 0x001b0840, 41}, + { 0x001b08ec, 10}, + { 0x001b0a40, 41}, + { 0x001b0aec, 10}, + { 0x001b0c40, 41}, + { 0x001b0cec, 10}, + { 0x001b0e40, 41}, + { 0x001b0eec, 10}, + { 0x001b4000, 1}, + { 0x001b4008, 1}, + { 0x001b4010, 3}, + { 0x001b4020, 3}, + { 0x001b4030, 3}, + { 0x001b4040, 3}, + { 0x001b4050, 3}, + { 0x001b4060, 4}, + { 0x001b4074, 7}, + { 0x001b4094, 3}, + { 0x001b40a4, 1}, + { 0x001b4100, 6}, + { 0x001b4128, 1}, + { 0x001b8000, 1}, + { 0x001b8008, 1}, + { 0x001b8010, 2}, + { 0x001bc000, 1}, + { 0x001bc008, 1}, + { 0x001bc010, 2}, + { 0x001be000, 1}, + { 0x001be008, 1}, + { 0x001be010, 2}, + { 0x00400500, 1}, + { 0x0040415c, 1}, + { 0x00404468, 1}, + { 0x00404498, 1}, + { 0x00405800, 1}, + { 0x00405840, 2}, + { 0x00405850, 1}, + { 0x00405908, 1}, + { 0x00405b40, 1}, + { 0x00405b50, 1}, + { 0x00406024, 5}, + { 0x00407010, 1}, + { 0x00407808, 1}, + { 0x0040803c, 1}, + { 0x00408804, 1}, + { 0x0040880c, 1}, + { 0x00408900, 2}, + { 0x00408910, 1}, + { 0x00408944, 1}, + { 0x00408984, 1}, + { 0x004090a8, 1}, + { 0x004098a0, 1}, + { 0x00409b00, 1}, + { 0x0041000c, 1}, + { 0x00410110, 1}, + { 0x00410184, 1}, + { 0x0041040c, 1}, + { 0x00410510, 1}, + { 0x00410584, 1}, + { 0x00418000, 1}, + { 0x00418008, 1}, + { 0x00418380, 2}, + { 0x00418400, 2}, + { 0x004184a0, 1}, + { 0x00418604, 1}, + { 0x00418680, 1}, + { 0x00418704, 1}, + { 0x00418714, 1}, + { 0x00418800, 1}, + { 0x0041881c, 1}, + { 0x00418830, 1}, + { 0x00418884, 1}, + { 0x004188b0, 1}, + { 0x004188c8, 3}, + { 0x004188fc, 1}, + { 0x00418b04, 1}, + { 0x00418c04, 1}, + { 0x00418c10, 8}, + { 0x00418c88, 1}, + { 0x00418d00, 1}, + { 0x00418e00, 1}, + { 0x00418e08, 1}, + { 0x00418e34, 1}, + { 0x00418e40, 4}, + { 0x00418e58, 16}, + { 0x00418f08, 1}, + { 0x00419000, 1}, + { 0x0041900c, 1}, + { 0x00419018, 1}, + { 0x00419854, 1}, + { 0x00419864, 1}, + { 0x00419a04, 2}, + { 0x00419a14, 1}, + { 0x00419ab0, 1}, + { 0x00419ab8, 3}, + { 0x00419c0c, 1}, + { 0x00419c8c, 2}, + { 0x00419d00, 1}, + { 0x00419d08, 2}, + { 0x00419e00, 11}, + { 0x00419e34, 2}, + { 0x00419e44, 11}, + { 0x00419e74, 10}, + { 0x00419ea4, 1}, + { 0x00419eac, 2}, + { 0x00419ee8, 1}, + { 0x00419ef0, 28}, + { 0x00419f70, 1}, + { 0x00419f78, 2}, + { 0x00419f98, 2}, + { 0x0041a02c, 2}, + { 0x0041a0a8, 1}, + { 0x0041a8a0, 3}, + { 0x0041b014, 1}, + { 0x0041b0a0, 1}, + { 0x0041b0cc, 1}, + { 0x0041b1dc, 1}, + { 0x0041be0c, 3}, + { 0x0041bea0, 1}, + { 0x0041becc, 1}, + { 0x0041bfdc, 1}, + { 0x0041c054, 1}, + { 0x0041c2b0, 1}, + { 0x0041c2b8, 3}, + { 0x0041c40c, 1}, + { 0x0041c48c, 2}, + { 0x0041c500, 1}, + { 0x0041c508, 2}, + { 0x0041c600, 11}, + { 0x0041c634, 2}, + { 0x0041c644, 11}, + { 0x0041c674, 10}, + { 0x0041c6a4, 1}, + { 0x0041c6ac, 2}, + { 0x0041c6e8, 1}, + { 0x0041c6f0, 28}, + { 0x0041c770, 1}, + { 0x0041c778, 2}, + { 0x0041c798, 2}, + { 0x0041c854, 1}, + { 0x0041cab0, 1}, + { 0x0041cab8, 3}, + { 0x0041cc0c, 1}, + { 0x0041cc8c, 2}, + { 0x0041cd00, 1}, + { 0x0041cd08, 2}, + { 0x0041ce00, 11}, + { 0x0041ce34, 2}, + { 0x0041ce44, 11}, + { 0x0041ce74, 10}, + { 0x0041cea4, 1}, + { 0x0041ceac, 2}, + { 0x0041cee8, 1}, + { 0x0041cef0, 28}, + { 0x0041cf70, 1}, + { 0x0041cf78, 2}, + { 0x0041cf98, 2}, + { 0x00500384, 1}, + { 0x005004a0, 1}, + { 0x00500604, 1}, + { 0x00500680, 1}, + { 0x00500714, 1}, + { 0x0050081c, 1}, + { 0x00500884, 1}, + { 0x005008b0, 1}, + { 0x005008c8, 3}, + { 0x005008fc, 1}, + { 0x00500b04, 1}, + { 0x00500c04, 1}, + { 0x00500c10, 8}, + { 0x00500c88, 1}, + { 0x00500d00, 1}, + { 0x00500e08, 1}, + { 0x00500f08, 1}, + { 0x00501000, 1}, + { 0x0050100c, 1}, + { 0x00501018, 1}, + { 0x00501854, 1}, + { 0x00501ab0, 1}, + { 0x00501ab8, 3}, + { 0x00501c0c, 1}, + { 0x00501c8c, 2}, + { 0x00501d00, 1}, + { 0x00501d08, 2}, + { 0x00501e00, 11}, + { 0x00501e34, 2}, + { 0x00501e44, 11}, + { 0x00501e74, 10}, + { 0x00501ea4, 1}, + { 0x00501eac, 2}, + { 0x00501ee8, 1}, + { 0x00501ef0, 28}, + { 0x00501f70, 1}, + { 0x00501f78, 2}, + { 0x00501f98, 2}, + { 0x0050202c, 2}, + { 0x005020a8, 1}, + { 0x005028a0, 3}, + { 0x00503014, 1}, + { 0x005030a0, 1}, + { 0x005030cc, 1}, + { 0x005031dc, 1}, + { 0x00503e14, 1}, + { 0x00503ea0, 1}, + { 0x00503ecc, 1}, + { 0x00503fdc, 1}, + { 0x00504054, 1}, + { 0x005042b0, 1}, + { 0x005042b8, 3}, + { 0x0050440c, 1}, + { 0x0050448c, 2}, + { 0x00504500, 1}, + { 0x00504508, 2}, + { 0x00504600, 11}, + { 0x00504634, 2}, + { 0x00504644, 11}, + { 0x00504674, 10}, + { 0x005046a4, 1}, + { 0x005046ac, 2}, + { 0x005046e8, 1}, + { 0x005046f0, 28}, + { 0x00504770, 1}, + { 0x00504778, 2}, + { 0x00504798, 2}, + { 0x00504854, 1}, + { 0x00504ab0, 1}, + { 0x00504ab8, 3}, + { 0x00504c0c, 1}, + { 0x00504c8c, 2}, + { 0x00504d00, 1}, + { 0x00504d08, 2}, + { 0x00504e00, 11}, + { 0x00504e34, 2}, + { 0x00504e44, 11}, + { 0x00504e74, 10}, + { 0x00504ea4, 1}, + { 0x00504eac, 2}, + { 0x00504ee8, 1}, + { 0x00504ef0, 28}, + { 0x00504f70, 1}, + { 0x00504f78, 2}, + { 0x00504f98, 2}, + { 0x00900100, 1}, + { 0x009a0100, 1},}; + + +static const u32 gv100_global_whitelist_ranges_count = + ARRAY_SIZE(gv100_global_whitelist_ranges); + +/* context */ + +/* runcontrol */ +static const u32 gv100_runcontrol_whitelist[] = { +}; +static const u32 gv100_runcontrol_whitelist_count = + ARRAY_SIZE(gv100_runcontrol_whitelist); + +static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = { +}; +static const u32 gv100_runcontrol_whitelist_ranges_count = + ARRAY_SIZE(gv100_runcontrol_whitelist_ranges); + + +/* quad ctl */ +static const u32 gv100_qctl_whitelist[] = { +}; +static const u32 gv100_qctl_whitelist_count = + ARRAY_SIZE(gv100_qctl_whitelist); + +static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = { +}; +static const u32 gv100_qctl_whitelist_ranges_count = + ARRAY_SIZE(gv100_qctl_whitelist_ranges); + +const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) +{ + return gv100_global_whitelist_ranges; +} + +int gv100_get_global_whitelist_ranges_count(void) +{ + return gv100_global_whitelist_ranges_count; +} + +const struct regop_offset_range *gv100_get_context_whitelist_ranges(void) +{ + return gv100_global_whitelist_ranges; +} + +int gv100_get_context_whitelist_ranges_count(void) +{ + return gv100_global_whitelist_ranges_count; +} + +const u32 *gv100_get_runcontrol_whitelist(void) +{ + return gv100_runcontrol_whitelist; +} + +int gv100_get_runcontrol_whitelist_count(void) +{ + return gv100_runcontrol_whitelist_count; +} + +const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void) +{ + return gv100_runcontrol_whitelist_ranges; +} + +int gv100_get_runcontrol_whitelist_ranges_count(void) +{ + return gv100_runcontrol_whitelist_ranges_count; +} + +const u32 *gv100_get_qctl_whitelist(void) +{ + return gv100_qctl_whitelist; +} + +int gv100_get_qctl_whitelist_count(void) +{ + return gv100_qctl_whitelist_count; +} + +const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void) +{ + return gv100_qctl_whitelist_ranges; +} + +int gv100_get_qctl_whitelist_ranges_count(void) +{ + return gv100_qctl_whitelist_ranges_count; +} + +int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s) +{ + /* Not needed on gv100 */ + return 0; +} diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.h b/drivers/gpu/nvgpu/gv100/regops_gv100.h new file mode 100644 index 00000000..06e5b8e1 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.h @@ -0,0 +1,42 @@ +/* + * + * Tegra GV100 GPU Driver Register Ops + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __REGOPS_GV100_H_ +#define __REGOPS_GV100_H_ + +const struct regop_offset_range *gv100_get_global_whitelist_ranges(void); +int gv100_get_global_whitelist_ranges_count(void); +const struct regop_offset_range *gv100_get_context_whitelist_ranges(void); +int gv100_get_context_whitelist_ranges_count(void); +const u32 *gv100_get_runcontrol_whitelist(void); +int gv100_get_runcontrol_whitelist_count(void); +const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void); +int gv100_get_runcontrol_whitelist_ranges_count(void); +const u32 *gv100_get_qctl_whitelist(void); +int gv100_get_qctl_whitelist_count(void); +const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void); +int gv100_get_qctl_whitelist_ranges_count(void); +int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s); + +#endif /* __REGOPS_GV11B_H_ */ -- cgit v1.2.2 From 0899e11d4bb630381607a0c245f72476e2e9209e Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 6 Oct 2017 17:20:12 -0700 Subject: gpu: nvgpu: Cleanup generic MM code t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 3a8dc4b1..1ae424df 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -535,6 +535,7 @@ static const struct gpu_ops gv100_ops = { .init_pdb = gp10b_mm_init_pdb, .init_mm_setup_hw = gv11b_init_mm_setup_hw, .is_bar1_supported = gv11b_mm_is_bar1_supported, + .alloc_inst_block = gk20a_alloc_inst_block, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, .get_kind_invalid = gm20b_get_kind_invalid, -- cgit v1.2.2 From c6ccb5f2a1e9a8999436f6c28ed5c416c5418ae3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 23 Oct 2017 10:20:12 -0700 Subject: gpu: nvgpu: gv11b: use scg perf for smid numbering For SCG to work, smid numbering needs to be done based on scg performance of tpcs. For gv11b and gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table" to do this. Used local variable "index" to avoid multiple computations in the function: gr_gv100_init_sm_id_table index = sm_id + sm Add deug info for printing initialized gpc/tpc/sm/global_tpc indexs. Bug 1842197 Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1583916 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 4b2038ba..8a4b88b4 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -251,12 +251,19 @@ void gr_gv100_init_sm_id_table(struct gk20a *g) for (tpc = 0, sm_id = 0; sm_id < num_sm; tpc++, sm_id += sm_per_tpc) { for (sm = 0; sm < sm_per_tpc; sm++) { - g->gr.sm_to_cluster[sm_id + sm].gpc_index = - gpc_table[tpc]; - g->gr.sm_to_cluster[sm_id + sm].tpc_index = - tpc_table[tpc]; - g->gr.sm_to_cluster[sm_id + sm].sm_index = sm; - g->gr.sm_to_cluster[sm_id + sm].global_tpc_index = tpc; + u32 index = sm_id + sm; + + g->gr.sm_to_cluster[index].gpc_index = gpc_table[tpc]; + g->gr.sm_to_cluster[index].tpc_index = tpc_table[tpc]; + g->gr.sm_to_cluster[index].sm_index = sm; + g->gr.sm_to_cluster[index].global_tpc_index = tpc; + nvgpu_log_info(g, + "gpc : %d tpc %d sm_index %d global_index: %d", + g->gr.sm_to_cluster[index].gpc_index, + g->gr.sm_to_cluster[index].tpc_index, + g->gr.sm_to_cluster[index].sm_index, + g->gr.sm_to_cluster[index].global_tpc_index); + } } -- cgit v1.2.2 From 1cbb5ea0235f15180b1d4299499cab85db23c5ce Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 13 Oct 2017 17:15:46 -0700 Subject: gpu: nvgpu: init_cyclestats fixes - in the native case, replace calls for init_cyclestats with the gm20b version, as each chip had identical versions of the code. - in the virtual case, use the vgpu version of the function in order to get the new max_css_buffer_size characteristic set to the mempool size. JIRA ESRM-54 Bug 200296210 Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1578934 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 1ae424df..e8be1a43 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -316,7 +316,7 @@ static const struct gpu_ops gv100_ops = { .get_max_fbps_count = gr_gm20b_get_max_fbps_count, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .wait_empty = gr_gv11b_wait_empty, - .init_cyclestats = gr_gv11b_init_cyclestats, + .init_cyclestats = gr_gm20b_init_cyclestats, .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, .bpt_reg_info = gv11b_gr_bpt_reg_info, -- cgit v1.2.2 From 938785f1525ce0ae654c2be0911e15816617995d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 23 Oct 2017 08:45:13 -0700 Subject: gpu: nvgpu: Linux specific GPU characteristics flags Make GPU characteristics flags specific to Linux code only. The rest of driver is moved to using nvgpu_is_enabled() API. JIRA NVGPU-259 Change-Id: I46a5a90bb34f170e9e755e7683be142ed6b18cce Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1583992 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e8be1a43..e51b4446 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -107,6 +107,7 @@ #include #include #include +#include #include #include @@ -221,16 +222,13 @@ static int gv100_get_litter_value(struct gk20a *g, int value) int gv100_init_gpu_characteristics(struct gk20a *g) { - struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; - int err; err = gk20a_init_gpu_characteristics(g); if (err) return err; - gpu->flags |= - NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); return 0; } -- cgit v1.2.2 From 20294264468eecc8c1a065aa83d5f1b46ff07e7e Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 23 Oct 2017 14:01:28 -0700 Subject: gpu: nvgpu: gv1xx: resize patch buffer Follow the sizing consideration in bug 1753763 to support dynamic TPC modes and subcontexts. bug 200350539 Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1584034 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 53 +++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/gr_gv100.h | 2 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 3 files changed, 55 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 8a4b88b4..430c7cd0 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -294,3 +294,56 @@ void gr_gv100_load_tpc_mask(struct gk20a *g) gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask)); gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask)); } + +u32 gr_gv100_get_patch_slots(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + struct fifo_gk20a *f = &g->fifo; + u32 size = 0; + + /* + * CMD to update PE table + */ + size++; + + /* + * Update PE table contents + * for PE table, each patch buffer update writes 32 TPCs + */ + size += DIV_ROUND_UP(gr->tpc_count, 32); + + /* + * Update the PL table contents + * For PL table, each patch buffer update configures 4 TPCs + */ + size += DIV_ROUND_UP(gr->tpc_count, 4); + + /* + * We need this for all subcontexts + */ + size *= f->t19x.max_subctx_count; + + /* + * Add space for a partition mode change as well + * reserve two slots since DYNAMIC -> STATIC requires + * DYNAMIC -> NONE -> STATIC + */ + size += 2; + + /* + * Add current patch buffer size + */ + size += gr_gk20a_get_patch_slots(g); + + /* + * Align to 4K size + */ + size = ALIGN(size, PATCH_CTX_SLOTS_PER_PAGE); + + /* + * Increase the size to accommodate for additional TPC partition update + */ + size += 2 * PATCH_CTX_SLOTS_PER_PAGE; + + return size; +} diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index 460b05ae..612f76f9 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -32,5 +32,5 @@ void gr_gv100_init_sm_id_table(struct gk20a *g); void gr_gv100_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv100_load_smid_config(struct gk20a *g); - +u32 gr_gv100_get_patch_slots(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e51b4446..61e9e46d 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -261,6 +261,7 @@ static const struct gpu_ops gv100_ops = { .get_num_pce = gv11b_ce_get_num_pce, }, .gr = { + .get_patch_slots = gr_gv100_get_patch_slots, .init_gpc_mmu = gr_gv11b_init_gpc_mmu, .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, .cb_size_default = gr_gv100_cb_size_default, -- cgit v1.2.2 From afd1649cfcae97e873663586d55f9a4cfd671808 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 26 Oct 2017 15:20:39 -0700 Subject: gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linux Fixups for the change of name subject in nvgpu. JIRA NVGPU-287 Change-Id: I6c19733079061a42786b94fc48db374d715ccbef Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1586548 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 61e9e46d..0950409f 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -709,7 +709,9 @@ int gv100_init_hal(struct gk20a *g) gops->fifo = gv100_ops.fifo; gops->gr_ctx = gv100_ops.gr_ctx; gops->mm = gv100_ops.mm; +#ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = gv100_ops.fecs_trace; +#endif gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; gops->pmu = gv100_ops.pmu; -- cgit v1.2.2 From 39cc741a02067e00f0003649dcd45285eb4640a5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sun, 29 Oct 2017 20:17:50 -0700 Subject: gpu: nvgpu: Add GPU arch and impl to common structure Add GPU architecture and implementation to a new struct nvgpu_gpu_params which is defined in common header file gk20a/gk20.h. JIRA NVGPU-259 Change-Id: Idde2caded75fcb1e03e95be11f6aa2ec33a0962b Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1588033 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c index 9f13abce..8b50125e 100644 --- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -27,7 +27,7 @@ int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name) { - u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; + u32 ver = g->params.gpu_arch + g->params.gpu_impl; switch (ver) { case NVGPU_GPUID_GV100: -- cgit v1.2.2 From f472922b3582dbba78b633958a4cb7b65ddb3f03 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 31 Oct 2017 12:23:30 -0700 Subject: gpu: nvgpu: Split ctxsw_trace API into non-Linux component T19x component for similar change in the main nvgpu code. JIRA NVGPU-287 Change-Id: Ib126b3d1fb562850fbb3ab89103f2a7fdaa13306 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1589430 Reviewed-by: Terje Bergstrom Reviewed-by: svc-mobile-coverity Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 0950409f..30b8e2c3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -30,7 +30,6 @@ #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" -#include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" @@ -108,6 +107,7 @@ #include #include #include +#include #include #include -- cgit v1.2.2 From 5b368d3e46b946ed2a6b1b70ad2ac600740e582a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 10:47:20 -0800 Subject: gpu: nvgpu: gv1xx: Move fuse override DT handling Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Ic672e25090cdfc207d9771ab61b6cf53185113a4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593693 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 30b8e2c3..4ee333b5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -334,7 +334,6 @@ static const struct gpu_ops gv100_ops = { .suspend_contexts = gr_gp10b_suspend_contexts, .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, - .fuse_override = gp10b_gr_fuse_override, .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, -- cgit v1.2.2 From c87e85af0cd812c6e1c138d4d1e48c23e3aa6bd3 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 09:31:37 -0800 Subject: gpu: nvgpu: Return GPU classes in get_litter_value Return GPU classes in HAL get_litter_value() instead of assigning them to GPU characteristics at HAL initialization time. JIRA NVGPU-259 Change-Id: I92cbadf3bd07292a8715d30843972def879795f5 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593691 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4ee333b5..88008e77 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -213,6 +213,24 @@ static int gv100_get_litter_value(struct gk20a *g, int value) case GPU_LIT_SMPC_PRI_STRIDE: ret = proj_smpc_stride_v(); break; + case GPU_LIT_TWOD_CLASS: + ret = FERMI_TWOD_A; + break; + case GPU_LIT_THREED_CLASS: + ret = VOLTA_A; + break; + case GPU_LIT_COMPUTE_CLASS: + ret = VOLTA_COMPUTE_A; + break; + case GPU_LIT_GPFIFO_CLASS: + ret = VOLTA_CHANNEL_GPFIFO_A; + break; + case GPU_LIT_I2M_CLASS: + ret = KEPLER_INLINE_TO_MEMORY_B; + break; + case GPU_LIT_DMA_COPY_CLASS: + ret = VOLTA_DMA_COPY_A; + break; default: break; } @@ -697,7 +715,6 @@ static const struct gpu_ops gv100_ops = { int gv100_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; gops->bios = gv100_ops.bios; gops->ltc = gv100_ops.ltc; @@ -754,12 +771,5 @@ int gv100_init_hal(struct gk20a *g) g->name = "gv10x"; - c->twod_class = FERMI_TWOD_A; - c->threed_class = VOLTA_A; - c->compute_class = VOLTA_COMPUTE_A; - c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = VOLTA_DMA_COPY_A; - return 0; } -- cgit v1.2.2 From 98bd673a7371940f24d37ad3a6d7b426995e737e Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Fri, 15 Sep 2017 18:58:58 +0300 Subject: gpu: nvgpu: Remove PTE kind code for GV100/GV11B Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and the related kind setup code. They are not needed anymore. While we're doing these changes, remove a redundant assignment of g->bootstrap_owner in hal_gv100.c. Bug 1902982 Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd Signed-off-by: Sami Kiminki Reviewed-on: https://git-master.nvidia.com/r/1560931 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 88008e77..7f2b149b 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -764,11 +764,6 @@ int gv100_init_hal(struct gk20a *g) g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); - - g->bootstrap_owner = LSF_FALCON_ID_SEC2; - g->name = "gv10x"; return 0; -- cgit v1.2.2 From af5e4a1bf63037e7618adfa11a950244df5883f2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 15 Nov 2017 15:10:51 +0530 Subject: gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLs TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using combination of timeslice and interleave levels to decide the priority Hence remove the IOCTLs and all corresponding APIs Jira NVGPU-393 Change-Id: Idce925631653784e39864223dc418a99a7e7ca3c Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1598582 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7f2b149b..4044c4b5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -449,7 +449,6 @@ static const struct gpu_ops gv100_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gv11b_setup_ramfc, - .channel_set_priority = gk20a_fifo_set_priority, .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, -- cgit v1.2.2