diff options
author | Tejal Kudav <tkudav@nvidia.com> | 2018-08-21 03:16:53 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-10 07:54:00 -0400 |
commit | 66f7bcc2f841f43e9bcd2a854361d6783bdb030e (patch) | |
tree | fd7ac3e76e45caf9d3a6b2082139a89c51c6d88a /drivers/gpu/nvgpu/gv100 | |
parent | b026c012963b135f8689c4409d12e79a76bb1156 (diff) |
gpu: nvgpu: Add Top as a unit
NVHSCLK registers used by NVLINK IP are part of dev_top
hardware headers. This patch adds "Top" as a separate
unit and exposes HALs to access dev_top registers. The top
unit contains top-level configuration information and any
extra registers or features that do not fit into another block's
feature set.
JIRA NVGPU-1053
JIRA NVGPU-966
Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803632
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 25 |
2 files changed, 26 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9d90d1d4..589f6adf 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #include "common/fuse/fuse_gm20b.h" | 44 | #include "common/fuse/fuse_gm20b.h" |
45 | #include "common/fuse/fuse_gp10b.h" | 45 | #include "common/fuse/fuse_gp10b.h" |
46 | #include "common/fuse/fuse_gp106.h" | 46 | #include "common/fuse/fuse_gp106.h" |
47 | #include "common/top/top_gv100.h" | ||
47 | 48 | ||
48 | #include "gk20a/gk20a.h" | 49 | #include "gk20a/gk20a.h" |
49 | #include "gk20a/fifo_gk20a.h" | 50 | #include "gk20a/fifo_gk20a.h" |
@@ -926,6 +927,16 @@ static const struct gpu_ops gv100_ops = { | |||
926 | .early_init = gv100_nvlink_early_init, | 927 | .early_init = gv100_nvlink_early_init, |
927 | }, | 928 | }, |
928 | #endif | 929 | #endif |
930 | .top = { | ||
931 | .get_nvhsclk_ctrl_e_clk_nvl = | ||
932 | gv100_top_get_nvhsclk_ctrl_e_clk_nvl, | ||
933 | .set_nvhsclk_ctrl_e_clk_nvl = | ||
934 | gv100_top_set_nvhsclk_ctrl_e_clk_nvl, | ||
935 | .get_nvhsclk_ctrl_swap_clk_nvl = | ||
936 | gv100_top_get_nvhsclk_ctrl_swap_clk_nvl, | ||
937 | .set_nvhsclk_ctrl_swap_clk_nvl = | ||
938 | gv100_top_set_nvhsclk_ctrl_swap_clk_nvl, | ||
939 | }, | ||
929 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, | 940 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, |
930 | .get_litter_value = gv100_get_litter_value, | 941 | .get_litter_value = gv100_get_litter_value, |
931 | }; | 942 | }; |
@@ -964,6 +975,7 @@ int gv100_init_hal(struct gk20a *g) | |||
964 | gops->priv_ring = gv100_ops.priv_ring; | 975 | gops->priv_ring = gv100_ops.priv_ring; |
965 | gops->fuse = gv100_ops.fuse; | 976 | gops->fuse = gv100_ops.fuse; |
966 | gops->nvlink = gv100_ops.nvlink; | 977 | gops->nvlink = gv100_ops.nvlink; |
978 | gops->top = gv100_ops.top; | ||
967 | 979 | ||
968 | /* clocks */ | 980 | /* clocks */ |
969 | gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; | 981 | gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; |
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index 3e1b2cda..7457c181 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -1461,7 +1461,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1461 | u32 i; | 1461 | u32 i; |
1462 | u32 links_off; | 1462 | u32 links_off; |
1463 | struct nvgpu_timeout timeout; | 1463 | struct nvgpu_timeout timeout; |
1464 | u32 pad_ctrl, swap_ctrl; | 1464 | u32 pad_ctrl = 0; |
1465 | u32 swap_ctrl = 0; | ||
1465 | u32 pll_id; | 1466 | u32 pll_id; |
1466 | 1467 | ||
1467 | reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); | 1468 | reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); |
@@ -1469,10 +1470,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1469 | trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1)); | 1470 | trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1)); |
1470 | gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg); | 1471 | gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg); |
1471 | 1472 | ||
1472 | reg = gk20a_readl(g, top_nvhsclk_ctrl_r()); | 1473 | if (g->ops.top.get_nvhsclk_ctrl_e_clk_nvl) { |
1473 | 1474 | pad_ctrl = g->ops.top.get_nvhsclk_ctrl_e_clk_nvl(g); | |
1474 | pad_ctrl = top_nvhsclk_ctrl_e_clk_nvl_v(reg); | 1475 | } |
1475 | swap_ctrl = top_nvhsclk_ctrl_swap_clk_nvl_v(reg); | 1476 | if (g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl) { |
1477 | swap_ctrl = g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl(g); | ||
1478 | } | ||
1476 | 1479 | ||
1477 | for_each_set_bit(i, &link_mask, 32) { | 1480 | for_each_set_bit(i, &link_mask, 32) { |
1478 | /* There are 3 PLLs for 6 links. We have 3 bits for each PLL. | 1481 | /* There are 3 PLLs for 6 links. We have 3 bits for each PLL. |
@@ -1483,12 +1486,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1483 | swap_ctrl |= BIT(pll_id); | 1486 | swap_ctrl |= BIT(pll_id); |
1484 | } | 1487 | } |
1485 | 1488 | ||
1486 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), | 1489 | if (g->ops.top.set_nvhsclk_ctrl_e_clk_nvl) { |
1487 | top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl)); | 1490 | g->ops.top.set_nvhsclk_ctrl_e_clk_nvl(g, pad_ctrl); |
1488 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), | 1491 | } |
1489 | top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl)); | 1492 | if (g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl) { |
1490 | 1493 | g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl(g, swap_ctrl); | |
1491 | gk20a_writel(g, top_nvhsclk_ctrl_r(), reg); | 1494 | } |
1492 | 1495 | ||
1493 | for_each_set_bit(i, &link_mask, 32) { | 1496 | for_each_set_bit(i, &link_mask, 32) { |
1494 | reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i)); | 1497 | reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i)); |