From 66f7bcc2f841f43e9bcd2a854361d6783bdb030e Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Tue, 21 Aug 2018 12:46:53 +0530 Subject: gpu: nvgpu: Add Top as a unit NVHSCLK registers used by NVLINK IP are part of dev_top hardware headers. This patch adds "Top" as a separate unit and exposes HALs to access dev_top registers. The top unit contains top-level configuration information and any extra registers or features that do not fit into another block's feature set. JIRA NVGPU-1053 JIRA NVGPU-966 Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916 Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/1803632 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 12 ++++++++++++ drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 25 ++++++++++++++----------- 2 files changed, 26 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9d90d1d4..589f6adf 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -44,6 +44,7 @@ #include "common/fuse/fuse_gm20b.h" #include "common/fuse/fuse_gp10b.h" #include "common/fuse/fuse_gp106.h" +#include "common/top/top_gv100.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -926,6 +927,16 @@ static const struct gpu_ops gv100_ops = { .early_init = gv100_nvlink_early_init, }, #endif + .top = { + .get_nvhsclk_ctrl_e_clk_nvl = + gv100_top_get_nvhsclk_ctrl_e_clk_nvl, + .set_nvhsclk_ctrl_e_clk_nvl = + gv100_top_set_nvhsclk_ctrl_e_clk_nvl, + .get_nvhsclk_ctrl_swap_clk_nvl = + gv100_top_get_nvhsclk_ctrl_swap_clk_nvl, + .set_nvhsclk_ctrl_swap_clk_nvl = + gv100_top_set_nvhsclk_ctrl_swap_clk_nvl, + }, .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, .get_litter_value = gv100_get_litter_value, }; @@ -964,6 +975,7 @@ int gv100_init_hal(struct gk20a *g) gops->priv_ring = gv100_ops.priv_ring; gops->fuse = gv100_ops.fuse; gops->nvlink = gv100_ops.nvlink; + gops->top = gv100_ops.top; /* clocks */ gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index 3e1b2cda..7457c181 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c @@ -1461,7 +1461,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) u32 i; u32 links_off; struct nvgpu_timeout timeout; - u32 pad_ctrl, swap_ctrl; + u32 pad_ctrl = 0; + u32 swap_ctrl = 0; u32 pll_id; reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); @@ -1469,10 +1470,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1)); gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg); - reg = gk20a_readl(g, top_nvhsclk_ctrl_r()); - - pad_ctrl = top_nvhsclk_ctrl_e_clk_nvl_v(reg); - swap_ctrl = top_nvhsclk_ctrl_swap_clk_nvl_v(reg); + if (g->ops.top.get_nvhsclk_ctrl_e_clk_nvl) { + pad_ctrl = g->ops.top.get_nvhsclk_ctrl_e_clk_nvl(g); + } + if (g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl) { + swap_ctrl = g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl(g); + } for_each_set_bit(i, &link_mask, 32) { /* There are 3 PLLs for 6 links. We have 3 bits for each PLL. @@ -1483,12 +1486,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) swap_ctrl |= BIT(pll_id); } - reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), - top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl)); - reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), - top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl)); - - gk20a_writel(g, top_nvhsclk_ctrl_r(), reg); + if (g->ops.top.set_nvhsclk_ctrl_e_clk_nvl) { + g->ops.top.set_nvhsclk_ctrl_e_clk_nvl(g, pad_ctrl); + } + if (g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl) { + g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl(g, swap_ctrl); + } for_each_set_bit(i, &link_mask, 32) { reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i)); -- cgit v1.2.2