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authorDeepak Nibade <dnibade@nvidia.com>2018-09-04 07:07:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-05 23:41:36 -0400
commit2998ab4e0a0b19da1332b82d779bd17b4e284b38 (patch)
treee86e3201c1920f8cb0afecdb6e21f9c0bf8de366 /drivers/gpu/nvgpu/gp10b
parent2b2bde04e14135cae5f7433c755e6b8d70f88abb (diff)
gpu: nvgpu: remove unused regops HALs
Below regops HALs are not being called from anywhere, so remove them gops.regops.get_runcontrol_whitelist_ranges() gops.regops.get_runcontrol_whitelist_ranges_count() gops.regops.get_qctl_whitelist_ranges() gops.regops.get_qctl_whitelist_ranges_count() HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it was originally only needed for gk20a which is not unsupported So remove this HAL and its call too Jira NVGPU-620 Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c8
-rw-r--r--drivers/gpu/nvgpu/gp10b/regops_gp10b.c40
2 files changed, 0 insertions, 48 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 321a89fd..af64d2a9 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -626,16 +626,8 @@ static const struct gpu_ops gp10b_ops = {
626 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, 626 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
627 .get_runcontrol_whitelist_count = 627 .get_runcontrol_whitelist_count =
628 gp10b_get_runcontrol_whitelist_count, 628 gp10b_get_runcontrol_whitelist_count,
629 .get_runcontrol_whitelist_ranges =
630 gp10b_get_runcontrol_whitelist_ranges,
631 .get_runcontrol_whitelist_ranges_count =
632 gp10b_get_runcontrol_whitelist_ranges_count,
633 .get_qctl_whitelist = gp10b_get_qctl_whitelist, 629 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
634 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, 630 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
635 .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
636 .get_qctl_whitelist_ranges_count =
637 gp10b_get_qctl_whitelist_ranges_count,
638 .apply_smpc_war = gp10b_apply_smpc_war,
639 }, 631 },
640 .mc = { 632 .mc = {
641 .intr_mask = mc_gp10b_intr_mask, 633 .intr_mask = mc_gp10b_intr_mask,
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
index 8113f7d5..c61709e0 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
@@ -23,12 +23,9 @@
23 */ 23 */
24 24
25#include "gk20a/gk20a.h" 25#include "gk20a/gk20a.h"
26#include "gk20a/dbg_gpu_gk20a.h"
27#include "gk20a/regops_gk20a.h" 26#include "gk20a/regops_gk20a.h"
28#include "regops_gp10b.h" 27#include "regops_gp10b.h"
29 28
30#include <nvgpu/bsearch.h>
31
32static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { 29static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {
33 { 0x000004f0, 1}, 30 { 0x000004f0, 1},
34 { 0x00001a00, 3}, 31 { 0x00001a00, 3},
@@ -393,23 +390,12 @@ static const u32 gp10b_runcontrol_whitelist[] = {
393static const u64 gp10b_runcontrol_whitelist_count = 390static const u64 gp10b_runcontrol_whitelist_count =
394 ARRAY_SIZE(gp10b_runcontrol_whitelist); 391 ARRAY_SIZE(gp10b_runcontrol_whitelist);
395 392
396static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = {
397};
398static const u64 gp10b_runcontrol_whitelist_ranges_count =
399 ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges);
400
401
402/* quad ctl */ 393/* quad ctl */
403static const u32 gp10b_qctl_whitelist[] = { 394static const u32 gp10b_qctl_whitelist[] = {
404}; 395};
405static const u64 gp10b_qctl_whitelist_count = 396static const u64 gp10b_qctl_whitelist_count =
406 ARRAY_SIZE(gp10b_qctl_whitelist); 397 ARRAY_SIZE(gp10b_qctl_whitelist);
407 398
408static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = {
409};
410static const u64 gp10b_qctl_whitelist_ranges_count =
411 ARRAY_SIZE(gp10b_qctl_whitelist_ranges);
412
413const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) 399const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
414{ 400{
415 return gp10b_global_whitelist_ranges; 401 return gp10b_global_whitelist_ranges;
@@ -440,16 +426,6 @@ u64 gp10b_get_runcontrol_whitelist_count(void)
440 return gp10b_runcontrol_whitelist_count; 426 return gp10b_runcontrol_whitelist_count;
441} 427}
442 428
443const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
444{
445 return gp10b_runcontrol_whitelist_ranges;
446}
447
448u64 gp10b_get_runcontrol_whitelist_ranges_count(void)
449{
450 return gp10b_runcontrol_whitelist_ranges_count;
451}
452
453const u32 *gp10b_get_qctl_whitelist(void) 429const u32 *gp10b_get_qctl_whitelist(void)
454{ 430{
455 return gp10b_qctl_whitelist; 431 return gp10b_qctl_whitelist;
@@ -459,19 +435,3 @@ u64 gp10b_get_qctl_whitelist_count(void)
459{ 435{
460 return gp10b_qctl_whitelist_count; 436 return gp10b_qctl_whitelist_count;
461} 437}
462
463const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
464{
465 return gp10b_qctl_whitelist_ranges;
466}
467
468u64 gp10b_get_qctl_whitelist_ranges_count(void)
469{
470 return gp10b_qctl_whitelist_ranges_count;
471}
472
473int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
474{
475 /* Not needed on gp10b */
476 return 0;
477}