From 2998ab4e0a0b19da1332b82d779bd17b4e284b38 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 4 Sep 2018 16:37:33 +0530 Subject: gpu: nvgpu: remove unused regops HALs Below regops HALs are not being called from anywhere, so remove them gops.regops.get_runcontrol_whitelist_ranges() gops.regops.get_runcontrol_whitelist_ranges_count() gops.regops.get_qctl_whitelist_ranges() gops.regops.get_qctl_whitelist_ranges_count() HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it was originally only needed for gk20a which is not unsupported So remove this HAL and its call too Jira NVGPU-620 Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1813106 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 8 ------- drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 40 ---------------------------------- 2 files changed, 48 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 321a89fd..af64d2a9 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -626,16 +626,8 @@ static const struct gpu_ops gp10b_ops = { .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, .get_runcontrol_whitelist_count = gp10b_get_runcontrol_whitelist_count, - .get_runcontrol_whitelist_ranges = - gp10b_get_runcontrol_whitelist_ranges, - .get_runcontrol_whitelist_ranges_count = - gp10b_get_runcontrol_whitelist_ranges_count, .get_qctl_whitelist = gp10b_get_qctl_whitelist, .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, - .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges, - .get_qctl_whitelist_ranges_count = - gp10b_get_qctl_whitelist_ranges_count, - .apply_smpc_war = gp10b_apply_smpc_war, }, .mc = { .intr_mask = mc_gp10b_intr_mask, diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c index 8113f7d5..c61709e0 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c @@ -23,12 +23,9 @@ */ #include "gk20a/gk20a.h" -#include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/regops_gk20a.h" #include "regops_gp10b.h" -#include - static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { { 0x000004f0, 1}, { 0x00001a00, 3}, @@ -393,23 +390,12 @@ static const u32 gp10b_runcontrol_whitelist[] = { static const u64 gp10b_runcontrol_whitelist_count = ARRAY_SIZE(gp10b_runcontrol_whitelist); -static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = { -}; -static const u64 gp10b_runcontrol_whitelist_ranges_count = - ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges); - - /* quad ctl */ static const u32 gp10b_qctl_whitelist[] = { }; static const u64 gp10b_qctl_whitelist_count = ARRAY_SIZE(gp10b_qctl_whitelist); -static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { -}; -static const u64 gp10b_qctl_whitelist_ranges_count = - ARRAY_SIZE(gp10b_qctl_whitelist_ranges); - const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) { return gp10b_global_whitelist_ranges; @@ -440,16 +426,6 @@ u64 gp10b_get_runcontrol_whitelist_count(void) return gp10b_runcontrol_whitelist_count; } -const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) -{ - return gp10b_runcontrol_whitelist_ranges; -} - -u64 gp10b_get_runcontrol_whitelist_ranges_count(void) -{ - return gp10b_runcontrol_whitelist_ranges_count; -} - const u32 *gp10b_get_qctl_whitelist(void) { return gp10b_qctl_whitelist; @@ -459,19 +435,3 @@ u64 gp10b_get_qctl_whitelist_count(void) { return gp10b_qctl_whitelist_count; } - -const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) -{ - return gp10b_qctl_whitelist_ranges; -} - -u64 gp10b_get_qctl_whitelist_ranges_count(void) -{ - return gp10b_qctl_whitelist_ranges_count; -} - -int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) -{ - /* Not needed on gp10b */ - return 0; -} -- cgit v1.2.2