summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-09 12:20:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-14 18:33:20 -0400
commit91390d857f6302f9c2923ec4188ea7e24ee537a2 (patch)
treee0884e79ea748d2c0bd384c29f805125a7b88fec /drivers/gpu/nvgpu/gp10b/therm_gp10b.c
parent02f9c99e4b4a452ded20978c5ee1e27b775b9224 (diff)
gpu: nvgpu: Move therm HAL to common
Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/therm_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/therm_gp10b.c137
1 files changed, 0 insertions, 137 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
deleted file mode 100644
index 905ff178..00000000
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * GP10B Therm
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "therm_gp10b.h"
27
28#include <nvgpu/soc.h>
29#include <nvgpu/io.h>
30#include <nvgpu/utils.h>
31
32#include <nvgpu/hw/gp10b/hw_therm_gp10b.h>
33
34int gp10b_init_therm_setup_hw(struct gk20a *g)
35{
36 u32 v;
37
38 nvgpu_log_fn(g, " ");
39
40 /* program NV_THERM registers */
41 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
42 therm_use_a_ext_therm_1_enable_f() |
43 therm_use_a_ext_therm_2_enable_f());
44 gk20a_writel(g, therm_evt_ext_therm_0_r(),
45 therm_evt_ext_therm_0_slow_factor_f(0x2));
46 gk20a_writel(g, therm_evt_ext_therm_1_r(),
47 therm_evt_ext_therm_1_slow_factor_f(0x6));
48 gk20a_writel(g, therm_evt_ext_therm_2_r(),
49 therm_evt_ext_therm_2_slow_factor_f(0xe));
50
51 gk20a_writel(g, therm_grad_stepping_table_r(0),
52 therm_grad_stepping_table_slowdown_factor0_f(
53 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
54 therm_grad_stepping_table_slowdown_factor1_f(
55 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
56 therm_grad_stepping_table_slowdown_factor2_f(
57 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
58 therm_grad_stepping_table_slowdown_factor3_f(
59 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
60 therm_grad_stepping_table_slowdown_factor4_f(
61 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
62
63 gk20a_writel(g, therm_grad_stepping_table_r(1),
64 therm_grad_stepping_table_slowdown_factor0_f(
65 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
66 therm_grad_stepping_table_slowdown_factor1_f(
67 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
68 therm_grad_stepping_table_slowdown_factor2_f(
69 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
70 therm_grad_stepping_table_slowdown_factor3_f(
71 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
72 therm_grad_stepping_table_slowdown_factor4_f(
73 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
74
75 v = gk20a_readl(g, therm_clk_timing_r(0));
76 v |= therm_clk_timing_grad_slowdown_enabled_f();
77 gk20a_writel(g, therm_clk_timing_r(0), v);
78
79 v = gk20a_readl(g, therm_config2_r());
80 v |= therm_config2_grad_enable_f(1);
81 v |= therm_config2_slowdown_factor_extended_f(1);
82 gk20a_writel(g, therm_config2_r(), v);
83
84 gk20a_writel(g, therm_grad_stepping1_r(),
85 therm_grad_stepping1_pdiv_duration_f(32));
86
87 v = gk20a_readl(g, therm_grad_stepping0_r());
88 v |= therm_grad_stepping0_feature_enable_f();
89 gk20a_writel(g, therm_grad_stepping0_r(), v);
90
91 return 0;
92}
93
94int gp10b_elcg_init_idle_filters(struct gk20a *g)
95{
96 u32 gate_ctrl, idle_filter;
97 u32 engine_id;
98 u32 active_engine_id = 0;
99 struct fifo_gk20a *f = &g->fifo;
100
101 nvgpu_log_fn(g, " ");
102
103 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
104 active_engine_id = f->active_engines_list[engine_id];
105 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
106
107 if (nvgpu_platform_is_simulation(g)) {
108 gate_ctrl = set_field(gate_ctrl,
109 therm_gate_ctrl_eng_delay_after_m(),
110 therm_gate_ctrl_eng_delay_after_f(4));
111 }
112
113 /* 2 * (1 << 9) = 1024 clks */
114 gate_ctrl = set_field(gate_ctrl,
115 therm_gate_ctrl_eng_idle_filt_exp_m(),
116 therm_gate_ctrl_eng_idle_filt_exp_f(9));
117 gate_ctrl = set_field(gate_ctrl,
118 therm_gate_ctrl_eng_idle_filt_mant_m(),
119 therm_gate_ctrl_eng_idle_filt_mant_f(2));
120 gate_ctrl = set_field(gate_ctrl,
121 therm_gate_ctrl_eng_delay_before_m(),
122 therm_gate_ctrl_eng_delay_before_f(4));
123 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
124 }
125
126 /* default fecs_idle_filter to 0 */
127 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
128 idle_filter &= ~therm_fecs_idle_filter_value_m();
129 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
130 /* default hubmmu_idle_filter to 0 */
131 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
132 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
133 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
134
135 nvgpu_log_fn(g, "done");
136 return 0;
137}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:48:58 -0400