From 91390d857f6302f9c2923ec4188ea7e24ee537a2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 9 Aug 2018 09:20:33 -0700 Subject: gpu: nvgpu: Move therm HAL to common Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/therm_gp10b.c | 137 ---------------------------------- 1 file changed, 137 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gp10b/therm_gp10b.c (limited to 'drivers/gpu/nvgpu/gp10b/therm_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c deleted file mode 100644 index 905ff178..00000000 --- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * GP10B Therm - * - * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" -#include "therm_gp10b.h" - -#include -#include -#include - -#include - -int gp10b_init_therm_setup_hw(struct gk20a *g) -{ - u32 v; - - nvgpu_log_fn(g, " "); - - /* program NV_THERM registers */ - gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() | - therm_use_a_ext_therm_1_enable_f() | - therm_use_a_ext_therm_2_enable_f()); - gk20a_writel(g, therm_evt_ext_therm_0_r(), - therm_evt_ext_therm_0_slow_factor_f(0x2)); - gk20a_writel(g, therm_evt_ext_therm_1_r(), - therm_evt_ext_therm_1_slow_factor_f(0x6)); - gk20a_writel(g, therm_evt_ext_therm_2_r(), - therm_evt_ext_therm_2_slow_factor_f(0xe)); - - gk20a_writel(g, therm_grad_stepping_table_r(0), - therm_grad_stepping_table_slowdown_factor0_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) | - therm_grad_stepping_table_slowdown_factor1_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) | - therm_grad_stepping_table_slowdown_factor2_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) | - therm_grad_stepping_table_slowdown_factor3_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor4_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); - - gk20a_writel(g, therm_grad_stepping_table_r(1), - therm_grad_stepping_table_slowdown_factor0_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor1_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor2_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor3_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor4_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); - - v = gk20a_readl(g, therm_clk_timing_r(0)); - v |= therm_clk_timing_grad_slowdown_enabled_f(); - gk20a_writel(g, therm_clk_timing_r(0), v); - - v = gk20a_readl(g, therm_config2_r()); - v |= therm_config2_grad_enable_f(1); - v |= therm_config2_slowdown_factor_extended_f(1); - gk20a_writel(g, therm_config2_r(), v); - - gk20a_writel(g, therm_grad_stepping1_r(), - therm_grad_stepping1_pdiv_duration_f(32)); - - v = gk20a_readl(g, therm_grad_stepping0_r()); - v |= therm_grad_stepping0_feature_enable_f(); - gk20a_writel(g, therm_grad_stepping0_r(), v); - - return 0; -} - -int gp10b_elcg_init_idle_filters(struct gk20a *g) -{ - u32 gate_ctrl, idle_filter; - u32 engine_id; - u32 active_engine_id = 0; - struct fifo_gk20a *f = &g->fifo; - - nvgpu_log_fn(g, " "); - - for (engine_id = 0; engine_id < f->num_engines; engine_id++) { - active_engine_id = f->active_engines_list[engine_id]; - gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); - - if (nvgpu_platform_is_simulation(g)) { - gate_ctrl = set_field(gate_ctrl, - therm_gate_ctrl_eng_delay_after_m(), - therm_gate_ctrl_eng_delay_after_f(4)); - } - - /* 2 * (1 << 9) = 1024 clks */ - gate_ctrl = set_field(gate_ctrl, - therm_gate_ctrl_eng_idle_filt_exp_m(), - therm_gate_ctrl_eng_idle_filt_exp_f(9)); - gate_ctrl = set_field(gate_ctrl, - therm_gate_ctrl_eng_idle_filt_mant_m(), - therm_gate_ctrl_eng_idle_filt_mant_f(2)); - gate_ctrl = set_field(gate_ctrl, - therm_gate_ctrl_eng_delay_before_m(), - therm_gate_ctrl_eng_delay_before_f(4)); - gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); - } - - /* default fecs_idle_filter to 0 */ - idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r()); - idle_filter &= ~therm_fecs_idle_filter_value_m(); - gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter); - /* default hubmmu_idle_filter to 0 */ - idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r()); - idle_filter &= ~therm_hubmmu_idle_filter_value_m(); - gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); - - nvgpu_log_fn(g, "done"); - return 0; -} -- cgit v1.2.2