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| author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-05-25 13:27:10 -0400 |
|---|---|---|
| committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:07 -0400 |
| commit | 27694ca572c4d7698b107c6713f0f0604b41c186 (patch) | |
| tree | 60dc8a1a8518797fd95f82d1e02892a984911667 /drivers/gpu/nvgpu/gp10b/mm_gp10b.h | |
| parent | 5c8f1619ce5ab1cf46484c8914fa29bcc208b9a0 (diff) | |
gpu: nvgpu: Implement bus HAL for bar2 bind
Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL.
BAR2 bind HW API is in bus.
JIRA NVGPU-588
Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730896
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.h')
| -rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 5522d02e..4f37aae6 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h | |||
| @@ -32,7 +32,6 @@ u32 gp10b_mm_get_default_big_page_size(void); | |||
| 32 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g); | 32 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g); |
| 33 | int gp10b_init_mm_setup_hw(struct gk20a *g); | 33 | int gp10b_init_mm_setup_hw(struct gk20a *g); |
| 34 | int gp10b_init_bar2_vm(struct gk20a *g); | 34 | int gp10b_init_bar2_vm(struct gk20a *g); |
| 35 | int gp10b_init_bar2_mm_hw_setup(struct gk20a *g); | ||
| 36 | const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, | 35 | const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, |
| 37 | u32 big_page_size); | 36 | u32 big_page_size); |
| 38 | void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | 37 | void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, |