From 27694ca572c4d7698b107c6713f0f0604b41c186 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 25 May 2018 10:27:10 -0700 Subject: gpu: nvgpu: Implement bus HAL for bar2 bind Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL. BAR2 bind HW API is in bus. JIRA NVGPU-588 Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730896 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 5522d02e..4f37aae6 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -32,7 +32,6 @@ u32 gp10b_mm_get_default_big_page_size(void); u32 gp10b_mm_get_iommu_bit(struct gk20a *g); int gp10b_init_mm_setup_hw(struct gk20a *g); int gp10b_init_bar2_vm(struct gk20a *g); -int gp10b_init_bar2_mm_hw_setup(struct gk20a *g); const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, u32 big_page_size); void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, -- cgit v1.2.2