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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-06-07 15:44:10 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-07 23:06:55 -0400
commitfc724baa4becf051b3e6647858a6ded90f1cee86 (patch)
tree8d70e917e1aa5b7bf2bc97e1bc03838e38156916 /drivers/gpu/nvgpu/gp10b/mc_gp10b.c
parent8efe596b01972c4efd39e709d51bd2e88a62d43f (diff)
gpu: nvgpu: Add MC HAL is_intr1_pending
Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit that is passed as parameter to is_intr1_pending. The API is passed contents of intr1 register and an engine number, and returns true if there's an interrupt pending for the engine. JIRA NVGPU-26 Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497870 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index bfc7a3d4..7ccea370 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -19,6 +19,7 @@
19#include "mc_gp10b.h" 19#include "mc_gp10b.h"
20 20
21#include <nvgpu/atomic.h> 21#include <nvgpu/atomic.h>
22#include <nvgpu/unit.h>
22 23
23#include <nvgpu/hw/gp10b/hw_mc_gp10b.h> 24#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
24 25
@@ -169,6 +170,30 @@ void mc_gp10b_intr_stall_resume(struct gk20a *g)
169 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); 170 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
170} 171}
171 172
173static bool mc_gp10b_is_intr1_pending(struct gk20a *g,
174 enum nvgpu_unit unit, u32 mc_intr_1)
175{
176 u32 mask = 0;
177 bool is_pending;
178
179 switch (unit) {
180 case NVGPU_UNIT_FIFO:
181 mask = mc_intr_pfifo_pending_f();
182 break;
183 default:
184 break;
185 }
186
187 if (mask == 0) {
188 nvgpu_err(g, "unknown unit %d", unit);
189 is_pending = false;
190 } else {
191 is_pending = (mc_intr_1 & mask) ? true : false;
192 }
193
194 return is_pending;
195}
196
172void gp10b_init_mc(struct gpu_ops *gops) 197void gp10b_init_mc(struct gpu_ops *gops)
173{ 198{
174 gops->mc.intr_enable = mc_gp10b_intr_enable; 199 gops->mc.intr_enable = mc_gp10b_intr_enable;
@@ -184,4 +209,5 @@ void gp10b_init_mc(struct gpu_ops *gops)
184 gops->mc.disable = gk20a_mc_disable; 209 gops->mc.disable = gk20a_mc_disable;
185 gops->mc.reset = gk20a_mc_reset; 210 gops->mc.reset = gk20a_mc_reset;
186 gops->mc.boot_0 = gk20a_mc_boot_0; 211 gops->mc.boot_0 = gk20a_mc_boot_0;
212 gops->mc.is_intr1_pending = mc_gp10b_is_intr1_pending;
187} 213}