From fc724baa4becf051b3e6647858a6ded90f1cee86 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 7 Jun 2017 12:44:10 -0700 Subject: gpu: nvgpu: Add MC HAL is_intr1_pending Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit that is passed as parameter to is_intr1_pending. The API is passed contents of intr1 register and an engine number, and returns true if there's an interrupt pending for the engine. JIRA NVGPU-26 Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1497870 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index bfc7a3d4..7ccea370 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -19,6 +19,7 @@ #include "mc_gp10b.h" #include +#include #include @@ -169,6 +170,30 @@ void mc_gp10b_intr_stall_resume(struct gk20a *g) g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); } +static bool mc_gp10b_is_intr1_pending(struct gk20a *g, + enum nvgpu_unit unit, u32 mc_intr_1) +{ + u32 mask = 0; + bool is_pending; + + switch (unit) { + case NVGPU_UNIT_FIFO: + mask = mc_intr_pfifo_pending_f(); + break; + default: + break; + } + + if (mask == 0) { + nvgpu_err(g, "unknown unit %d", unit); + is_pending = false; + } else { + is_pending = (mc_intr_1 & mask) ? true : false; + } + + return is_pending; +} + void gp10b_init_mc(struct gpu_ops *gops) { gops->mc.intr_enable = mc_gp10b_intr_enable; @@ -184,4 +209,5 @@ void gp10b_init_mc(struct gpu_ops *gops) gops->mc.disable = gk20a_mc_disable; gops->mc.reset = gk20a_mc_reset; gops->mc.boot_0 = gk20a_mc_boot_0; + gops->mc.is_intr1_pending = mc_gp10b_is_intr1_pending; } -- cgit v1.2.2