diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-02-24 19:14:03 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-07 03:10:44 -0500 |
commit | 35f0cf0efefe4a64ee25a5b118338b15e552dcb0 (patch) | |
tree | c23c4a62e154d83d1558d9d50681cf5bfd1b1899 /drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |
parent | d6ff5ef649ead7cf7caded5c7742efd7ad569a8a (diff) |
gpu: nvgpu: change stall intr handling order
-Handle pbus and priv stall interrupts first.
In general critical interrupts should be
handled before any other non critical ones.
-Dump info enabled with gpu_dbg_intr if priv_ring
interrupt is flagged by fmodel.
JIRA NVGPU-25
Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1311273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 76848159..3f066c37 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP20B master | 2 | * GP20B master |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -113,6 +113,12 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
113 | 113 | ||
114 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 114 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
115 | 115 | ||
116 | /* handle critical interrupts first */ | ||
117 | if (mc_intr_0 & mc_intr_pbus_pending_f()) | ||
118 | gk20a_pbus_isr(g); | ||
119 | if (mc_intr_0 & mc_intr_priv_ring_pending_f()) | ||
120 | gk20a_priv_ring_isr(g); | ||
121 | |||
116 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | 122 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { |
117 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | 123 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; |
118 | 124 | ||
@@ -137,12 +143,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
137 | gk20a_fifo_isr(g); | 143 | gk20a_fifo_isr(g); |
138 | if (mc_intr_0 & mc_intr_pmu_pending_f()) | 144 | if (mc_intr_0 & mc_intr_pmu_pending_f()) |
139 | gk20a_pmu_isr(g); | 145 | gk20a_pmu_isr(g); |
140 | if (mc_intr_0 & mc_intr_priv_ring_pending_f()) | ||
141 | gk20a_priv_ring_isr(g); | ||
142 | if (mc_intr_0 & mc_intr_ltc_pending_f()) | 146 | if (mc_intr_0 & mc_intr_ltc_pending_f()) |
143 | g->ops.ltc.isr(g); | 147 | g->ops.ltc.isr(g); |
144 | if (mc_intr_0 & mc_intr_pbus_pending_f()) | ||
145 | gk20a_pbus_isr(g); | ||
146 | 148 | ||
147 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 149 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
148 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 150 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); |