From 35f0cf0efefe4a64ee25a5b118338b15e552dcb0 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 24 Feb 2017 16:14:03 -0800 Subject: gpu: nvgpu: change stall intr handling order -Handle pbus and priv stall interrupts first. In general critical interrupts should be handled before any other non critical ones. -Dump info enabled with gpu_dbg_intr if priv_ring interrupt is flagged by fmodel. JIRA NVGPU-25 Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1311273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 76848159..3f066c37 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -1,7 +1,7 @@ /* * GP20B master * - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -113,6 +113,12 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); + /* handle critical interrupts first */ + if (mc_intr_0 & mc_intr_pbus_pending_f()) + gk20a_pbus_isr(g); + if (mc_intr_0 & mc_intr_priv_ring_pending_f()) + gk20a_priv_ring_isr(g); + for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { active_engine_id = g->fifo.active_engines_list[engine_id_idx]; @@ -137,12 +143,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_fifo_isr(g); if (mc_intr_0 & mc_intr_pmu_pending_f()) gk20a_pmu_isr(g); - if (mc_intr_0 & mc_intr_priv_ring_pending_f()) - gk20a_priv_ring_isr(g); if (mc_intr_0 & mc_intr_ltc_pending_f()) g->ops.ltc.isr(g); - if (mc_intr_0 & mc_intr_pbus_pending_f()) - gk20a_pbus_isr(g); gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); -- cgit v1.2.2