diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-10-27 03:47:25 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:02 -0500 |
commit | 07b7a534fa8d5e93420521fcb5e745acad386f00 (patch) | |
tree | f844c36ed9eea3731c5317cda19a1b7135e3e5b3 /drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | |
parent | 1f3b9d851a0beb716596040f77b1431cc1fd8670 (diff) |
gpu: nvgpu: Synchronize gp10b headers with gm20b
Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.
Bug 1567274
Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index 764c1b6c..b79758d2 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | |||
@@ -206,6 +206,10 @@ static inline u32 fifo_intr_en_0_r(void) | |||
206 | { | 206 | { |
207 | return 0x00002140; | 207 | return 0x00002140; |
208 | } | 208 | } |
209 | static inline u32 fifo_intr_en_0_sched_error_m(void) | ||
210 | { | ||
211 | return 0x1 << 8; | ||
212 | } | ||
209 | static inline u32 fifo_intr_en_1_r(void) | 213 | static inline u32 fifo_intr_en_1_r(void) |
210 | { | 214 | { |
211 | return 0x00002528; | 215 | return 0x00002528; |
@@ -346,10 +350,18 @@ static inline u32 fifo_preempt_type_channel_f(void) | |||
346 | { | 350 | { |
347 | return 0x0; | 351 | return 0x0; |
348 | } | 352 | } |
353 | static inline u32 fifo_preempt_type_tsg_f(void) | ||
354 | { | ||
355 | return 0x1000000; | ||
356 | } | ||
349 | static inline u32 fifo_preempt_chid_f(u32 v) | 357 | static inline u32 fifo_preempt_chid_f(u32 v) |
350 | { | 358 | { |
351 | return (v & 0xfff) << 0; | 359 | return (v & 0xfff) << 0; |
352 | } | 360 | } |
361 | static inline u32 fifo_preempt_id_f(u32 v) | ||
362 | { | ||
363 | return (v & 0xfff) << 0; | ||
364 | } | ||
353 | static inline u32 fifo_trigger_mmu_fault_r(u32 i) | 365 | static inline u32 fifo_trigger_mmu_fault_r(u32 i) |
354 | { | 366 | { |
355 | return 0x00002a30 + i*4; | 367 | return 0x00002a30 + i*4; |
@@ -382,6 +394,10 @@ static inline u32 fifo_engine_status_id_type_chid_v(void) | |||
382 | { | 394 | { |
383 | return 0x00000000; | 395 | return 0x00000000; |
384 | } | 396 | } |
397 | static inline u32 fifo_engine_status_id_type_tsgid_v(void) | ||
398 | { | ||
399 | return 0x00000001; | ||
400 | } | ||
385 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) | 401 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) |
386 | { | 402 | { |
387 | return (r >> 13) & 0x7; | 403 | return (r >> 13) & 0x7; |
@@ -466,6 +482,10 @@ static inline u32 fifo_pbdma_status_id_type_chid_v(void) | |||
466 | { | 482 | { |
467 | return 0x00000000; | 483 | return 0x00000000; |
468 | } | 484 | } |
485 | static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) | ||
486 | { | ||
487 | return 0x00000001; | ||
488 | } | ||
469 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) | 489 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) |
470 | { | 490 | { |
471 | return (r >> 13) & 0x7; | 491 | return (r >> 13) & 0x7; |