From 07b7a534fa8d5e93420521fcb5e745acad386f00 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 09:47:25 +0200 Subject: gpu: nvgpu: Synchronize gp10b headers with gm20b Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index 764c1b6c..b79758d2 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -206,6 +206,10 @@ static inline u32 fifo_intr_en_0_r(void) { return 0x00002140; } +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} static inline u32 fifo_intr_en_1_r(void) { return 0x00002528; @@ -346,10 +350,18 @@ static inline u32 fifo_preempt_type_channel_f(void) { return 0x0; } +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} static inline u32 fifo_preempt_chid_f(u32 v) { return (v & 0xfff) << 0; } +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} static inline u32 fifo_trigger_mmu_fault_r(u32 i) { return 0x00002a30 + i*4; @@ -382,6 +394,10 @@ static inline u32 fifo_engine_status_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} static inline u32 fifo_engine_status_ctx_status_v(u32 r) { return (r >> 13) & 0x7; @@ -466,6 +482,10 @@ static inline u32 fifo_pbdma_status_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} static inline u32 fifo_pbdma_status_chan_status_v(u32 r) { return (r >> 13) & 0x7; -- cgit v1.2.2