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authorseshendra Gadagottu <sgadagottu@nvidia.com>2018-01-18 14:02:08 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-22 18:29:54 -0500
commit193a2ed38ca51d898ac811820ab86237c84e18eb (patch)
treeda672582c2322fc91c7b5c600deb5a60f3068a8d /drivers/gpu/nvgpu/gp10b/gr_gp10b.h
parentf6d898656a6d7c197aa27ee53f5f0151fb6dfcf5 (diff)
gpu: nvgpu: add sw method for SET_BES_CROP_DEBUG4
Added sw method support for SET_BES_CROP_DEBUG4. In this sw method: CLAMP_FP_BLEND_TO_MAXVAL forces overflow and CLAMP_FP_BLEND_TO_INF blend results to clamp to FP maxval. Added support for this sw method in gp10b/gp106/gv11b and gv100. Bug 2046636 Change-Id: I3a9e97587aca76718f7f504ea3b853f87409092a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1641529 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.h')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 8d553d37..8f1ebb16 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -49,9 +49,13 @@ enum {
49#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 49#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
50#define NVC097_SET_SHADER_EXCEPTIONS 0x1528 50#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
51#define NVC097_SET_BES_CROP_DEBUG3 0x10c4 51#define NVC097_SET_BES_CROP_DEBUG3 0x10c4
52#define NVC097_SET_BES_CROP_DEBUG4 0x10b0
52#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 53#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
53#define NVC0C0_SET_RD_COALESCE 0x0228 54#define NVC0C0_SET_RD_COALESCE 0x0228
54 55
56#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0
57#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1
58
55int gr_gp10b_init_fs_state(struct gk20a *g); 59int gr_gp10b_init_fs_state(struct gk20a *g);
56int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, 60int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
57 struct nvgpu_mem *mem); 61 struct nvgpu_mem *mem);
@@ -85,6 +89,7 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
85u32 gr_gp10b_pagepool_default_size(struct gk20a *g); 89u32 gr_gp10b_pagepool_default_size(struct gk20a *g);
86int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g); 90int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g);
87void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data); 91void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data);
92void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data);
88int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, 93int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
89 u32 class_num, u32 offset, u32 data); 94 u32 class_num, u32 offset, u32 data);
90void gr_gp10b_cb_size_default(struct gk20a *g); 95void gr_gp10b_cb_size_default(struct gk20a *g);