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author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2018-01-09 17:33:51 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-10 11:47:07 -0500 |
commit | e9de95d7e0629c40b5ceb56c07de319bedd3339f (patch) | |
tree | d48300e7b5191f732eaa5105049c9e4bfc81f2e9 /drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |
parent | 0ac3ba2a99b745f577c752ebf9a6b4291730a36d (diff) |
gpu: nvgpu: use chip specific zbc_c/z format reg
Use chip specific gpcs_swdx_dss_zbc_c_format_reg
and gpcs_swdx_dss_zbc_z_format_reg. These registers
are different for gv11b/gv100 from gp10b/gp106.
Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9a7f4f97..68d18aa1 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -507,11 +507,18 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, | |||
507 | gr_gpcs_gcc_pagepool_total_pages_f(size), patch); | 507 | gr_gpcs_gcc_pagepool_total_pages_f(size), patch); |
508 | } | 508 | } |
509 | 509 | ||
510 | u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g) | ||
511 | { | ||
512 | return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(); | ||
513 | } | ||
514 | |||
510 | int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | 515 | int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, |
511 | struct zbc_entry *color_val, u32 index) | 516 | struct zbc_entry *color_val, u32 index) |
512 | { | 517 | { |
513 | u32 i; | 518 | u32 i; |
514 | u32 zbc_c; | 519 | u32 zbc_c; |
520 | u32 zbc_c_format_reg = | ||
521 | g->ops.gr.get_gpcs_swdx_dss_zbc_c_format_reg(g); | ||
515 | 522 | ||
516 | /* update l2 table */ | 523 | /* update l2 table */ |
517 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); | 524 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); |
@@ -554,18 +561,25 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | |||
554 | color_val->color_ds[2]); | 561 | color_val->color_ds[2]); |
555 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), | 562 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), |
556 | color_val->color_ds[3]); | 563 | color_val->color_ds[3]); |
557 | zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); | 564 | zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3)); |
558 | zbc_c &= ~(0x7f << ((index % 4) * 7)); | 565 | zbc_c &= ~(0x7f << ((index % 4) * 7)); |
559 | zbc_c |= color_val->format << ((index % 4) * 7); | 566 | zbc_c |= color_val->format << ((index % 4) * 7); |
560 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); | 567 | gk20a_writel_check(g, zbc_c_format_reg + (index & ~3), zbc_c); |
561 | 568 | ||
562 | return 0; | 569 | return 0; |
563 | } | 570 | } |
564 | 571 | ||
572 | u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g) | ||
573 | { | ||
574 | return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); | ||
575 | } | ||
576 | |||
565 | int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | 577 | int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, |
566 | struct zbc_entry *depth_val, u32 index) | 578 | struct zbc_entry *depth_val, u32 index) |
567 | { | 579 | { |
568 | u32 zbc_z; | 580 | u32 zbc_z; |
581 | u32 zbc_z_format_reg = | ||
582 | g->ops.gr.get_gpcs_swdx_dss_zbc_z_format_reg(g); | ||
569 | 583 | ||
570 | /* update l2 table */ | 584 | /* update l2 table */ |
571 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); | 585 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); |
@@ -592,10 +606,10 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | |||
592 | gr->zbc_dep_tbl[index].ref_cnt++; | 606 | gr->zbc_dep_tbl[index].ref_cnt++; |
593 | 607 | ||
594 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); | 608 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); |
595 | zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); | 609 | zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3)); |
596 | zbc_z &= ~(0x7f << (index % 4) * 7); | 610 | zbc_z &= ~(0x7f << (index % 4) * 7); |
597 | zbc_z |= depth_val->format << (index % 4) * 7; | 611 | zbc_z |= depth_val->format << (index % 4) * 7; |
598 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); | 612 | gk20a_writel(g, zbc_z_format_reg + (index & ~3), zbc_z); |
599 | 613 | ||
600 | return 0; | 614 | return 0; |
601 | } | 615 | } |