From e9de95d7e0629c40b5ceb56c07de319bedd3339f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 9 Jan 2018 14:33:51 -0800 Subject: gpu: nvgpu: use chip specific zbc_c/z format reg Use chip specific gpcs_swdx_dss_zbc_c_format_reg and gpcs_swdx_dss_zbc_z_format_reg. These registers are different for gv11b/gv100 from gp10b/gp106. Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1635091 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9a7f4f97..68d18aa1 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -507,11 +507,18 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, gr_gpcs_gcc_pagepool_total_pages_f(size), patch); } +u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g) +{ + return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(); +} + int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *color_val, u32 index) { u32 i; u32 zbc_c; + u32 zbc_c_format_reg = + g->ops.gr.get_gpcs_swdx_dss_zbc_c_format_reg(g); /* update l2 table */ g->ops.ltc.set_zbc_color_entry(g, color_val, index); @@ -554,18 +561,25 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, color_val->color_ds[2]); gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); - zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); + zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3)); zbc_c &= ~(0x7f << ((index % 4) * 7)); zbc_c |= color_val->format << ((index % 4) * 7); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); + gk20a_writel_check(g, zbc_c_format_reg + (index & ~3), zbc_c); return 0; } +u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g) +{ + return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); +} + int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index) { u32 zbc_z; + u32 zbc_z_format_reg = + g->ops.gr.get_gpcs_swdx_dss_zbc_z_format_reg(g); /* update l2 table */ g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); @@ -592,10 +606,10 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, gr->zbc_dep_tbl[index].ref_cnt++; gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); - zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); + zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3)); zbc_z &= ~(0x7f << (index % 4) * 7); zbc_z |= depth_val->format << (index % 4) * 7; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); + gk20a_writel(g, zbc_z_format_reg + (index & ~3), zbc_z); return 0; } -- cgit v1.2.2