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authorsmadhavan <smadhavan@nvidia.com>2018-09-11 03:21:19 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-25 00:17:51 -0400
commit9e5f456f2b784656b44233b5ce5fc0f05f71bb3d (patch)
treea2c2e4250f81dc94d584675af486018aed4c2570 /drivers/gpu/nvgpu/gp10b/ce_gp10b.h
parent3c3f80a687ae95c36341d9bf1753f63dfc4a06af (diff)
nvgpu: gp10b: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gp10b by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: If66863e568d74a0bc7473cf8decacece1e1069f3 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1819163 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ce_gp10b.h')
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
index 525599af..4fa27d1e 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -21,8 +21,8 @@
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24#ifndef __CE_GP10B_H__ 24#ifndef NVGPU_CE_GP10B_H
25#define __CE_GP10B_H__ 25#define NVGPU_CE_GP10B_H
26 26
27#include <nvgpu/types.h> 27#include <nvgpu/types.h>
28 28
@@ -31,4 +31,4 @@ struct gk20a;
31void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); 31void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
32u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); 32u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
33 33
34#endif /*__CE2_GP10B_H__*/ 34#endif /* NVGPU_CE_GP10B_H */