diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-26 13:47:16 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-27 19:34:43 -0400 |
commit | 6431ec360bf7b7baf6dd687b1525c40114ede189 (patch) | |
tree | f899b3e215bf87cc411cefaf54c9b6011e487eb4 /drivers/gpu/nvgpu/gp106 | |
parent | 9907b97985c47003a179c4357274b737cc0699ee (diff) |
gpu: nvgpu: Reorg gr_ctx HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
gr_ctx sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I783d8e8919d8694ad2aa0d285e4c5a2b62580f48
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527417
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 8 |
3 files changed, 12 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c index 3a49cc60..706ff7e0 100644 --- a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP106 Graphics Context | 2 | * GP106 Graphics Context |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,7 +16,7 @@ | |||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gr_ctx_gp106.h" | 17 | #include "gr_ctx_gp106.h" |
18 | 18 | ||
19 | static int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name) | 19 | int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name) |
20 | { | 20 | { |
21 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | 21 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; |
22 | 22 | ||
@@ -36,14 +36,7 @@ static int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name) | |||
36 | return 0; | 36 | return 0; |
37 | } | 37 | } |
38 | 38 | ||
39 | static bool gr_gp106_is_firmware_defined(void) | 39 | bool gr_gp106_is_firmware_defined(void) |
40 | { | 40 | { |
41 | return true; | 41 | return true; |
42 | } | 42 | } |
43 | |||
44 | void gp106_init_gr_ctx(struct gpu_ops *gops) | ||
45 | { | ||
46 | gops->gr_ctx.get_netlist_name = gr_gp106_get_netlist_name; | ||
47 | gops->gr_ctx.is_fw_defined = gr_gp106_is_firmware_defined; | ||
48 | gops->gr_ctx.use_dma_for_fw_bootstrap = false; | ||
49 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h index fef80abb..f1162f5e 100644 --- a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -22,6 +22,7 @@ | |||
22 | #define GP106_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_C | 22 | #define GP106_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_C |
23 | #define GP104_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D | 23 | #define GP104_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D |
24 | 24 | ||
25 | void gp106_init_gr_ctx(struct gpu_ops *gops); | 25 | int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name); |
26 | bool gr_gp106_is_firmware_defined(void); | ||
26 | 27 | ||
27 | #endif /*__GR_CTX_GP106_H__*/ | 28 | #endif /*__GR_CTX_GP106_H__*/ |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 227b22e6..763dab44 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -313,6 +313,10 @@ static const struct gpu_ops gp106_ops = { | |||
313 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, | 313 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, |
314 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | 314 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, |
315 | }, | 315 | }, |
316 | .gr_ctx = { | ||
317 | .get_netlist_name = gr_gp106_get_netlist_name, | ||
318 | .is_fw_defined = gr_gp106_is_firmware_defined, | ||
319 | }, | ||
316 | .mc = { | 320 | .mc = { |
317 | .intr_enable = mc_gp10b_intr_enable, | 321 | .intr_enable = mc_gp10b_intr_enable, |
318 | .intr_unit_config = mc_gp10b_intr_unit_config, | 322 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -403,6 +407,7 @@ int gp106_init_hal(struct gk20a *g) | |||
403 | gops->ce2 = gp106_ops.ce2; | 407 | gops->ce2 = gp106_ops.ce2; |
404 | gops->clock_gating = gp106_ops.clock_gating; | 408 | gops->clock_gating = gp106_ops.clock_gating; |
405 | gops->fifo = gp106_ops.fifo; | 409 | gops->fifo = gp106_ops.fifo; |
410 | gops->gr_ctx = gp106_ops.gr_ctx; | ||
406 | gops->mc = gp106_ops.mc; | 411 | gops->mc = gp106_ops.mc; |
407 | gops->debug = gp106_ops.debug; | 412 | gops->debug = gp106_ops.debug; |
408 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; | 413 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; |
@@ -421,6 +426,7 @@ int gp106_init_hal(struct gk20a *g) | |||
421 | gp106_ops.chip_init_gpu_characteristics; | 426 | gp106_ops.chip_init_gpu_characteristics; |
422 | gops->bios_init = gp106_ops.bios_init; | 427 | gops->bios_init = gp106_ops.bios_init; |
423 | 428 | ||
429 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
424 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 430 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
425 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 431 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
426 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 432 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
@@ -429,7 +435,6 @@ int gp106_init_hal(struct gk20a *g) | |||
429 | gp106_init_gr(g); | 435 | gp106_init_gr(g); |
430 | gp10b_init_fecs_trace_ops(gops); | 436 | gp10b_init_fecs_trace_ops(gops); |
431 | gp106_init_fb(gops); | 437 | gp106_init_fb(gops); |
432 | gp106_init_gr_ctx(gops); | ||
433 | gp106_init_mm(gops); | 438 | gp106_init_mm(gops); |
434 | gp106_init_pmu_ops(g); | 439 | gp106_init_pmu_ops(g); |
435 | gp106_init_clk_ops(gops); | 440 | gp106_init_clk_ops(gops); |
@@ -439,7 +444,6 @@ int gp106_init_hal(struct gk20a *g) | |||
439 | gp106_init_therm_ops(gops); | 444 | gp106_init_therm_ops(gops); |
440 | 445 | ||
441 | g->name = "gp10x"; | 446 | g->name = "gp10x"; |
442 | gops->gr_ctx.use_dma_for_fw_bootstrap = true; | ||
443 | 447 | ||
444 | c->twod_class = FERMI_TWOD_A; | 448 | c->twod_class = FERMI_TWOD_A; |
445 | c->threed_class = PASCAL_B; | 449 | c->threed_class = PASCAL_B; |