diff options
author | Srirangan <smadhavan@nvidia.com> | 2018-08-27 01:59:01 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-29 11:59:35 -0400 |
commit | e3710e5431d8f14f1b8c2812f5c1aeeb7bdaac1c (patch) | |
tree | 8a6498b12e10f6b391d3c5dd7c6ac7b340ca60b4 /drivers/gpu/nvgpu/gp106/sec2_gp106.c | |
parent | 2f97e683feed3c3ba3c8722c4f6ab7466bcef0c0 (diff) |
gpu: nvgpu: gp106: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I8493274995ed8de526902dd0ca0808b2972e28aa
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796806
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 6f60fe41..61424bfe 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -41,8 +41,9 @@ int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, | |||
41 | { | 41 | { |
42 | int status = 0; | 42 | int status = 0; |
43 | 43 | ||
44 | if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) | 44 | if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) { |
45 | status = -EBUSY; | 45 | status = -EBUSY; |
46 | } | ||
46 | 47 | ||
47 | return status; | 48 | return status; |
48 | } | 49 | } |
@@ -166,8 +167,9 @@ void init_pmu_setup_hw1(struct gk20a *g) | |||
166 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | 167 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); |
167 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | 168 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( |
168 | pmu, GK20A_PMU_DMAIDX_VIRT); | 169 | pmu, GK20A_PMU_DMAIDX_VIRT); |
169 | if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) | 170 | if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) { |
170 | g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); | 171 | g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); |
172 | } | ||
171 | 173 | ||
172 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | 174 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, |
173 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | 175 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), |
@@ -222,8 +224,9 @@ int init_sec2_setup_hw1(struct gk20a *g, | |||
222 | psec_fbif_transcfg_target_noncoherent_sysmem_f()); | 224 | psec_fbif_transcfg_target_noncoherent_sysmem_f()); |
223 | 225 | ||
224 | err = bl_bootstrap_sec2(pmu, desc, bl_sz); | 226 | err = bl_bootstrap_sec2(pmu, desc, bl_sz); |
225 | if (err) | 227 | if (err) { |
226 | return err; | 228 | return err; |
229 | } | ||
227 | 230 | ||
228 | return 0; | 231 | return 0; |
229 | } | 232 | } |