From e3710e5431d8f14f1b8c2812f5c1aeeb7bdaac1c Mon Sep 17 00:00:00 2001 From: Srirangan Date: Mon, 27 Aug 2018 11:29:01 +0530 Subject: gpu: nvgpu: gp106: Fix MISRA 15.6 violations MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I8493274995ed8de526902dd0ca0808b2972e28aa Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1796806 Reviewed-by: svc-misra-checker Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/sec2_gp106.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 6f60fe41..61424bfe 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -41,8 +41,9 @@ int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, { int status = 0; - if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) + if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) { status = -EBUSY; + } return status; } @@ -166,8 +167,9 @@ void init_pmu_setup_hw1(struct gk20a *g) g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( pmu, GK20A_PMU_DMAIDX_VIRT); - if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) + if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) { g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); + } nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), @@ -222,8 +224,9 @@ int init_sec2_setup_hw1(struct gk20a *g, psec_fbif_transcfg_target_noncoherent_sysmem_f()); err = bl_bootstrap_sec2(pmu, desc, bl_sz); - if (err) + if (err) { return err; + } return 0; } -- cgit v1.2.2