diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-09-06 11:14:27 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-24 11:11:49 -0400 |
commit | 5d30a5cda37ca349b4d9cb7e1985c7a0849001b6 (patch) | |
tree | 89a37078480d7cec42d9a8c7bc869aae8bb28279 /drivers/gpu/nvgpu/gp106/sec2_gp106.c | |
parent | 7465926ccdcdad87c22c788fe04fc11961df53ba (diff) |
gpu: nvgpu: ACR code refactor
-Created struct nvgpu_acr to hold acr module related member
within single struct which are currently spread across multiple structs
like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr to perform ACR specific operation,
currently ACR ops were part PMU which caused to have always dependence
on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
gk20a_remove_support() method, earlier acr cleanup was part of
pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
statically for chip currently in execution & assign ops to point to
needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
HAL for all chips to bootstrap ACR, earlier had 3 different function for
gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.
JIRA NVGPU-1148
Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 171 |
1 files changed, 30 insertions, 141 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index dec35a91..40823b69 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -32,167 +32,61 @@ | |||
32 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 32 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
33 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> | 33 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> |
34 | 34 | ||
35 | int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, | 35 | int gp106_sec2_reset(struct gk20a *g) |
36 | unsigned int timeout) | ||
37 | { | 36 | { |
38 | int status = 0; | 37 | nvgpu_log_fn(g, " "); |
39 | |||
40 | if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) { | ||
41 | status = -EBUSY; | ||
42 | } | ||
43 | 38 | ||
44 | return status; | 39 | gk20a_writel(g, psec_falcon_engine_r(), |
45 | } | 40 | pwr_falcon_engine_reset_true_f()); |
41 | nvgpu_udelay(10); | ||
42 | gk20a_writel(g, psec_falcon_engine_r(), | ||
43 | pwr_falcon_engine_reset_false_f()); | ||
46 | 44 | ||
47 | int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | 45 | nvgpu_log_fn(g, "done"); |
48 | { | 46 | return 0; |
49 | u32 data = 0; | ||
50 | int completion = 0; | ||
51 | |||
52 | completion = nvgpu_flcn_wait_for_halt(&g->sec2_flcn, timeout); | ||
53 | if (completion) { | ||
54 | nvgpu_err(g, "ACR boot timed out"); | ||
55 | goto exit; | ||
56 | } | ||
57 | |||
58 | g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, | ||
59 | FALCON_MAILBOX_1); | ||
60 | nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities); | ||
61 | data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); | ||
62 | if (data) { | ||
63 | nvgpu_err(g, "ACR boot failed, err %x", data); | ||
64 | completion = -EAGAIN; | ||
65 | goto exit; | ||
66 | } | ||
67 | |||
68 | init_pmu_setup_hw1(g); | ||
69 | |||
70 | exit: | ||
71 | if (completion) { | ||
72 | nvgpu_kill_task_pg_init(g); | ||
73 | nvgpu_pmu_state_change(g, PMU_STATE_OFF, false); | ||
74 | nvgpu_flcn_dump_stats(&g->sec2_flcn); | ||
75 | } | ||
76 | |||
77 | return completion; | ||
78 | } | 47 | } |
79 | 48 | ||
80 | int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, | 49 | static int sec2_flcn_bl_bootstrap(struct gk20a *g, |
81 | void *desc, u32 bl_sz) | 50 | struct nvgpu_falcon_bl_info *bl_info) |
82 | { | 51 | { |
83 | struct gk20a *g = gk20a_from_pmu(pmu); | ||
84 | struct mm_gk20a *mm = &g->mm; | 52 | struct mm_gk20a *mm = &g->mm; |
85 | struct nvgpu_falcon_bl_info bl_info; | 53 | u32 data = 0U; |
86 | u32 data = 0; | 54 | int err = 0U; |
87 | 55 | ||
88 | nvgpu_log_fn(g, " "); | 56 | nvgpu_log_fn(g, " "); |
89 | 57 | ||
90 | /* SEC2 Config */ | 58 | /* SEC2 Config */ |
91 | gk20a_writel(g, psec_falcon_itfen_r(), | 59 | gk20a_writel(g, psec_falcon_itfen_r(), |
92 | gk20a_readl(g, psec_falcon_itfen_r()) | | 60 | gk20a_readl(g, psec_falcon_itfen_r()) | |
93 | psec_falcon_itfen_ctxen_enable_f()); | 61 | psec_falcon_itfen_ctxen_enable_f()); |
94 | 62 | ||
95 | gk20a_writel(g, psec_falcon_nxtctx_r(), | 63 | gk20a_writel(g, psec_falcon_nxtctx_r(), |
96 | pwr_pmu_new_instblk_ptr_f( | 64 | pwr_pmu_new_instblk_ptr_f( |
97 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 65 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) | |
98 | pwr_pmu_new_instblk_valid_f(1) | | 66 | pwr_pmu_new_instblk_valid_f(1U) | |
99 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | 67 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, |
100 | pwr_pmu_new_instblk_target_sys_ncoh_f(), | 68 | pwr_pmu_new_instblk_target_sys_ncoh_f(), |
101 | pwr_pmu_new_instblk_target_sys_coh_f(), | 69 | pwr_pmu_new_instblk_target_sys_coh_f(), |
102 | pwr_pmu_new_instblk_target_fb_f())); | 70 | pwr_pmu_new_instblk_target_fb_f())); |
103 | 71 | ||
104 | data = gk20a_readl(g, psec_falcon_debug1_r()); | 72 | data = gk20a_readl(g, psec_falcon_debug1_r()); |
105 | data |= psec_falcon_debug1_ctxsw_mode_m(); | 73 | data |= psec_falcon_debug1_ctxsw_mode_m(); |
106 | gk20a_writel(g, psec_falcon_debug1_r(), data); | 74 | gk20a_writel(g, psec_falcon_debug1_r(), data); |
107 | 75 | ||
108 | data = gk20a_readl(g, psec_falcon_engctl_r()); | 76 | data = gk20a_readl(g, psec_falcon_engctl_r()); |
109 | data |= (1 << 3); | 77 | data |= (1U << 3U); |
110 | gk20a_writel(g, psec_falcon_engctl_r(), data); | 78 | gk20a_writel(g, psec_falcon_engctl_r(), data); |
111 | 79 | ||
112 | bl_info.bl_src = g->acr.hsbl_ucode.cpu_va; | 80 | err = nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info); |
113 | bl_info.bl_desc = desc; | ||
114 | bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); | ||
115 | bl_info.bl_size = bl_sz; | ||
116 | bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag; | ||
117 | nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, &bl_info); | ||
118 | 81 | ||
119 | return 0; | 82 | return err; |
120 | } | 83 | } |
121 | 84 | ||
122 | void init_pmu_setup_hw1(struct gk20a *g) | 85 | int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g, |
86 | struct hs_acr *acr_desc, | ||
87 | struct nvgpu_falcon_bl_info *bl_info) | ||
123 | { | 88 | { |
124 | struct mm_gk20a *mm = &g->mm; | 89 | u32 data = 0U; |
125 | struct nvgpu_pmu *pmu = &g->pmu; | ||
126 | |||
127 | /* PMU TRANSCFG */ | ||
128 | /* setup apertures - virtual */ | ||
129 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
130 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
131 | pwr_fbif_transcfg_target_local_fb_f()); | ||
132 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
133 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
134 | /* setup apertures - physical */ | ||
135 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
136 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
137 | pwr_fbif_transcfg_target_local_fb_f()); | ||
138 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
139 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
140 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
141 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
142 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
143 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
144 | |||
145 | /* PMU Config */ | ||
146 | gk20a_writel(g, pwr_falcon_itfen_r(), | ||
147 | gk20a_readl(g, pwr_falcon_itfen_r()) | | ||
148 | pwr_falcon_itfen_ctxen_enable_f()); | ||
149 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | ||
150 | pwr_pmu_new_instblk_ptr_f( | ||
151 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | ||
152 | pwr_pmu_new_instblk_valid_f(1) | | ||
153 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | ||
154 | pwr_pmu_new_instblk_target_sys_ncoh_f(), | ||
155 | pwr_pmu_new_instblk_target_sys_coh_f(), | ||
156 | pwr_pmu_new_instblk_target_fb_f())); | ||
157 | |||
158 | /*Copying pmu cmdline args*/ | ||
159 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0); | ||
160 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | ||
161 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | ||
162 | pmu, GK20A_PMU_TRACE_BUFSIZE); | ||
163 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | ||
164 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | ||
165 | pmu, GK20A_PMU_DMAIDX_VIRT); | ||
166 | if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) { | ||
167 | g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); | ||
168 | } | ||
169 | |||
170 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | ||
171 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | ||
172 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | ||
173 | |||
174 | } | ||
175 | |||
176 | int gp106_sec2_reset(struct gk20a *g) | ||
177 | { | ||
178 | nvgpu_log_fn(g, " "); | ||
179 | |||
180 | gk20a_writel(g, psec_falcon_engine_r(), | ||
181 | pwr_falcon_engine_reset_true_f()); | ||
182 | nvgpu_udelay(10); | ||
183 | gk20a_writel(g, psec_falcon_engine_r(), | ||
184 | pwr_falcon_engine_reset_false_f()); | ||
185 | |||
186 | nvgpu_log_fn(g, "done"); | ||
187 | return 0; | ||
188 | } | ||
189 | |||
190 | int init_sec2_setup_hw1(struct gk20a *g, | ||
191 | void *desc, u32 bl_sz) | ||
192 | { | ||
193 | struct nvgpu_pmu *pmu = &g->pmu; | ||
194 | int err; | ||
195 | u32 data = 0; | ||
196 | 90 | ||
197 | nvgpu_log_fn(g, " "); | 91 | nvgpu_log_fn(g, " "); |
198 | 92 | ||
@@ -219,10 +113,5 @@ int init_sec2_setup_hw1(struct gk20a *g, | |||
219 | psec_fbif_transcfg_mem_type_physical_f() | | 113 | psec_fbif_transcfg_mem_type_physical_f() | |
220 | psec_fbif_transcfg_target_noncoherent_sysmem_f()); | 114 | psec_fbif_transcfg_target_noncoherent_sysmem_f()); |
221 | 115 | ||
222 | err = bl_bootstrap_sec2(pmu, desc, bl_sz); | 116 | return sec2_flcn_bl_bootstrap(g, bl_info); |
223 | if (err) { | ||
224 | return err; | ||
225 | } | ||
226 | |||
227 | return 0; | ||
228 | } | 117 | } |