From 5d30a5cda37ca349b4d9cb7e1985c7a0849001b6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 6 Sep 2018 20:44:27 +0530 Subject: gpu: nvgpu: ACR code refactor -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/sec2_gp106.c | 171 ++++++----------------------------- 1 file changed, 30 insertions(+), 141 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index dec35a91..40823b69 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -32,167 +32,61 @@ #include #include -int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, - unsigned int timeout) +int gp106_sec2_reset(struct gk20a *g) { - int status = 0; - - if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) { - status = -EBUSY; - } + nvgpu_log_fn(g, " "); - return status; -} + gk20a_writel(g, psec_falcon_engine_r(), + pwr_falcon_engine_reset_true_f()); + nvgpu_udelay(10); + gk20a_writel(g, psec_falcon_engine_r(), + pwr_falcon_engine_reset_false_f()); -int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) -{ - u32 data = 0; - int completion = 0; - - completion = nvgpu_flcn_wait_for_halt(&g->sec2_flcn, timeout); - if (completion) { - nvgpu_err(g, "ACR boot timed out"); - goto exit; - } - - g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, - FALCON_MAILBOX_1); - nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities); - data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); - if (data) { - nvgpu_err(g, "ACR boot failed, err %x", data); - completion = -EAGAIN; - goto exit; - } - - init_pmu_setup_hw1(g); - -exit: - if (completion) { - nvgpu_kill_task_pg_init(g); - nvgpu_pmu_state_change(g, PMU_STATE_OFF, false); - nvgpu_flcn_dump_stats(&g->sec2_flcn); - } - - return completion; + nvgpu_log_fn(g, "done"); + return 0; } -int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, - void *desc, u32 bl_sz) +static int sec2_flcn_bl_bootstrap(struct gk20a *g, + struct nvgpu_falcon_bl_info *bl_info) { - struct gk20a *g = gk20a_from_pmu(pmu); struct mm_gk20a *mm = &g->mm; - struct nvgpu_falcon_bl_info bl_info; - u32 data = 0; + u32 data = 0U; + int err = 0U; nvgpu_log_fn(g, " "); /* SEC2 Config */ gk20a_writel(g, psec_falcon_itfen_r(), - gk20a_readl(g, psec_falcon_itfen_r()) | - psec_falcon_itfen_ctxen_enable_f()); + gk20a_readl(g, psec_falcon_itfen_r()) | + psec_falcon_itfen_ctxen_enable_f()); gk20a_writel(g, psec_falcon_nxtctx_r(), - pwr_pmu_new_instblk_ptr_f( - nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | - pwr_pmu_new_instblk_valid_f(1) | - nvgpu_aperture_mask(g, &mm->pmu.inst_block, - pwr_pmu_new_instblk_target_sys_ncoh_f(), - pwr_pmu_new_instblk_target_sys_coh_f(), - pwr_pmu_new_instblk_target_fb_f())); + pwr_pmu_new_instblk_ptr_f( + nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) | + pwr_pmu_new_instblk_valid_f(1U) | + nvgpu_aperture_mask(g, &mm->pmu.inst_block, + pwr_pmu_new_instblk_target_sys_ncoh_f(), + pwr_pmu_new_instblk_target_sys_coh_f(), + pwr_pmu_new_instblk_target_fb_f())); data = gk20a_readl(g, psec_falcon_debug1_r()); data |= psec_falcon_debug1_ctxsw_mode_m(); gk20a_writel(g, psec_falcon_debug1_r(), data); data = gk20a_readl(g, psec_falcon_engctl_r()); - data |= (1 << 3); + data |= (1U << 3U); gk20a_writel(g, psec_falcon_engctl_r(), data); - bl_info.bl_src = g->acr.hsbl_ucode.cpu_va; - bl_info.bl_desc = desc; - bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); - bl_info.bl_size = bl_sz; - bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag; - nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, &bl_info); + err = nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info); - return 0; + return err; } -void init_pmu_setup_hw1(struct gk20a *g) +int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g, + struct hs_acr *acr_desc, + struct nvgpu_falcon_bl_info *bl_info) { - struct mm_gk20a *mm = &g->mm; - struct nvgpu_pmu *pmu = &g->pmu; - - /* PMU TRANSCFG */ - /* setup apertures - virtual */ - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_local_fb_f()); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), - pwr_fbif_transcfg_mem_type_virtual_f()); - /* setup apertures - physical */ - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_local_fb_f()); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_coherent_sysmem_f()); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_noncoherent_sysmem_f()); - - /* PMU Config */ - gk20a_writel(g, pwr_falcon_itfen_r(), - gk20a_readl(g, pwr_falcon_itfen_r()) | - pwr_falcon_itfen_ctxen_enable_f()); - gk20a_writel(g, pwr_pmu_new_instblk_r(), - pwr_pmu_new_instblk_ptr_f( - nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | - pwr_pmu_new_instblk_valid_f(1) | - nvgpu_aperture_mask(g, &mm->pmu.inst_block, - pwr_pmu_new_instblk_target_sys_ncoh_f(), - pwr_pmu_new_instblk_target_sys_coh_f(), - pwr_pmu_new_instblk_target_fb_f())); - - /*Copying pmu cmdline args*/ - g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0); - g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); - g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( - pmu, GK20A_PMU_TRACE_BUFSIZE); - g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); - g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( - pmu, GK20A_PMU_DMAIDX_VIRT); - if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) { - g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); - } - - nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, - (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), - g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); - -} - -int gp106_sec2_reset(struct gk20a *g) -{ - nvgpu_log_fn(g, " "); - - gk20a_writel(g, psec_falcon_engine_r(), - pwr_falcon_engine_reset_true_f()); - nvgpu_udelay(10); - gk20a_writel(g, psec_falcon_engine_r(), - pwr_falcon_engine_reset_false_f()); - - nvgpu_log_fn(g, "done"); - return 0; -} - -int init_sec2_setup_hw1(struct gk20a *g, - void *desc, u32 bl_sz) -{ - struct nvgpu_pmu *pmu = &g->pmu; - int err; - u32 data = 0; + u32 data = 0U; nvgpu_log_fn(g, " "); @@ -219,10 +113,5 @@ int init_sec2_setup_hw1(struct gk20a *g, psec_fbif_transcfg_mem_type_physical_f() | psec_fbif_transcfg_target_noncoherent_sysmem_f()); - err = bl_bootstrap_sec2(pmu, desc, bl_sz); - if (err) { - return err; - } - - return 0; + return sec2_flcn_bl_bootstrap(g, bl_info); } -- cgit v1.2.2