diff options
author | Sunny He <suhe@nvidia.com> | 2017-08-01 20:10:42 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-21 16:06:07 -0400 |
commit | 5f010177de985c901c33c914efe70a8498a5974f (patch) | |
tree | 1b1a2ac1ab71608a0754a7eb64222f5d198e793c /drivers/gpu/nvgpu/gp106/hal_gp106.c | |
parent | b50b379c192714d0d08c3f2d33e90c95cf795253 (diff) |
gpu: nvgpu: Reorg pmu HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
pmu sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I8839ac99e87153637005e23b3013237f57275c54
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530982
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 49 |
1 files changed, 48 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 6a50be34..21d5fee3 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include "gk20a/regops_gk20a.h" | 26 | #include "gk20a/regops_gk20a.h" |
27 | #include "gk20a/mc_gk20a.h" | 27 | #include "gk20a/mc_gk20a.h" |
28 | #include "gk20a/fb_gk20a.h" | 28 | #include "gk20a/fb_gk20a.h" |
29 | #include "gk20a/pmu_gk20a.h" | ||
29 | 30 | ||
30 | #include "gp10b/ltc_gp10b.h" | 31 | #include "gp10b/ltc_gp10b.h" |
31 | #include "gp10b/gr_gp10b.h" | 32 | #include "gp10b/gr_gp10b.h" |
@@ -38,6 +39,7 @@ | |||
38 | #include "gp10b/priv_ring_gp10b.h" | 39 | #include "gp10b/priv_ring_gp10b.h" |
39 | #include "gp10b/fifo_gp10b.h" | 40 | #include "gp10b/fifo_gp10b.h" |
40 | #include "gp10b/fb_gp10b.h" | 41 | #include "gp10b/fb_gp10b.h" |
42 | #include "gp10b/pmu_gp10b.h" | ||
41 | 43 | ||
42 | #include "gp106/fifo_gp106.h" | 44 | #include "gp106/fifo_gp106.h" |
43 | #include "gp106/regops_gp106.h" | 45 | #include "gp106/regops_gp106.h" |
@@ -48,7 +50,10 @@ | |||
48 | #include "gm20b/mm_gm20b.h" | 50 | #include "gm20b/mm_gm20b.h" |
49 | #include "gm20b/pmu_gm20b.h" | 51 | #include "gm20b/pmu_gm20b.h" |
50 | #include "gm20b/fb_gm20b.h" | 52 | #include "gm20b/fb_gm20b.h" |
53 | #include "gm20b/acr_gm20b.h" | ||
51 | 54 | ||
55 | #include "gp106/acr_gp106.h" | ||
56 | #include "gp106/sec2_gp106.h" | ||
52 | #include "gp106/clk_gp106.h" | 57 | #include "gp106/clk_gp106.h" |
53 | #include "gp106/clk_arb_gp106.h" | 58 | #include "gp106/clk_arb_gp106.h" |
54 | #include "gp106/mclk_gp106.h" | 59 | #include "gp106/mclk_gp106.h" |
@@ -77,6 +82,7 @@ | |||
77 | #include <nvgpu/hw/gp106/hw_ram_gp106.h> | 82 | #include <nvgpu/hw/gp106/hw_ram_gp106.h> |
78 | #include <nvgpu/hw/gp106/hw_top_gp106.h> | 83 | #include <nvgpu/hw/gp106/hw_top_gp106.h> |
79 | #include <nvgpu/hw/gp106/hw_pram_gp106.h> | 84 | #include <nvgpu/hw/gp106/hw_pram_gp106.h> |
85 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | ||
80 | 86 | ||
81 | 87 | ||
82 | static int gp106_get_litter_value(struct gk20a *g, int value) | 88 | static int gp106_get_litter_value(struct gk20a *g, int value) |
@@ -398,6 +404,45 @@ static const struct gpu_ops gp106_ops = { | |||
398 | .get_internal_sensor_limits = gp106_get_internal_sensor_limits, | 404 | .get_internal_sensor_limits = gp106_get_internal_sensor_limits, |
399 | .configure_therm_alert = gp106_configure_therm_alert, | 405 | .configure_therm_alert = gp106_configure_therm_alert, |
400 | }, | 406 | }, |
407 | .pmu = { | ||
408 | .init_wpr_region = gm20b_pmu_init_acr, | ||
409 | .load_lsfalcon_ucode = gp106_load_falcon_ucode, | ||
410 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, | ||
411 | .is_priv_load = gp106_is_priv_load, | ||
412 | .prepare_ucode = gp106_prepare_ucode_blob, | ||
413 | .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, | ||
414 | .get_wpr = gp106_wpr_info, | ||
415 | .alloc_blob_space = gp106_alloc_blob_space, | ||
416 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, | ||
417 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, | ||
418 | .falcon_wait_for_halt = sec2_wait_for_halt, | ||
419 | .falcon_clear_halt_interrupt_status = | ||
420 | sec2_clear_halt_interrupt_status, | ||
421 | .init_falcon_setup_hw = init_sec2_setup_hw1, | ||
422 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
423 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
424 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
425 | .is_pmu_supported = gp106_is_pmu_supported, | ||
426 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, | ||
427 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | ||
428 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
429 | .pmu_is_lpwr_feature_supported = | ||
430 | gp106_pmu_is_lpwr_feature_supported, | ||
431 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
432 | .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, | ||
433 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
434 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
435 | .pmu_pg_param_post_init = nvgpu_lpwr_post_init, | ||
436 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
437 | .pmu_pg_init_param = gp106_pg_param_init, | ||
438 | .reset_engine = gp106_pmu_engine_reset, | ||
439 | .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, | ||
440 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
441 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
442 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | ||
443 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
444 | .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, | ||
445 | }, | ||
401 | .clk = { | 446 | .clk = { |
402 | .init_clk_support = gp106_init_clk_support, | 447 | .init_clk_support = gp106_init_clk_support, |
403 | .get_crystal_clk_hz = gp106_crystal_clk_hz, | 448 | .get_crystal_clk_hz = gp106_crystal_clk_hz, |
@@ -532,6 +577,7 @@ int gp106_init_hal(struct gk20a *g) | |||
532 | gops->mm = gp106_ops.mm; | 577 | gops->mm = gp106_ops.mm; |
533 | gops->pramin = gp106_ops.pramin; | 578 | gops->pramin = gp106_ops.pramin; |
534 | gops->therm = gp106_ops.therm; | 579 | gops->therm = gp106_ops.therm; |
580 | gops->pmu = gp106_ops.pmu; | ||
535 | /* | 581 | /* |
536 | * clk must be assigned member by member | 582 | * clk must be assigned member by member |
537 | * since some clk ops are assigned during probe prior to HAL init | 583 | * since some clk ops are assigned during probe prior to HAL init |
@@ -568,10 +614,11 @@ int gp106_init_hal(struct gk20a *g) | |||
568 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 614 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
569 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 615 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
570 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 616 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
617 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
571 | 618 | ||
619 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
572 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 620 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
573 | gp106_init_gr(g); | 621 | gp106_init_gr(g); |
574 | gp106_init_pmu_ops(g); | ||
575 | 622 | ||
576 | gp10b_init_uncompressed_kind_map(); | 623 | gp10b_init_uncompressed_kind_map(); |
577 | gp10b_init_kind_attr(); | 624 | gp10b_init_kind_attr(); |