From 5f010177de985c901c33c914efe70a8498a5974f Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 1 Aug 2017 17:10:42 -0700 Subject: gpu: nvgpu: Reorg pmu HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8839ac99e87153637005e23b3013237f57275c54 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530982 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp106/hal_gp106.c | 49 ++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 6a50be34..21d5fee3 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -26,6 +26,7 @@ #include "gk20a/regops_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/fb_gk20a.h" +#include "gk20a/pmu_gk20a.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/gr_gp10b.h" @@ -38,6 +39,7 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/pmu_gp10b.h" #include "gp106/fifo_gp106.h" #include "gp106/regops_gp106.h" @@ -48,7 +50,10 @@ #include "gm20b/mm_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/fb_gm20b.h" +#include "gm20b/acr_gm20b.h" +#include "gp106/acr_gp106.h" +#include "gp106/sec2_gp106.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" #include "gp106/mclk_gp106.h" @@ -77,6 +82,7 @@ #include #include #include +#include static int gp106_get_litter_value(struct gk20a *g, int value) @@ -398,6 +404,45 @@ static const struct gpu_ops gp106_ops = { .get_internal_sensor_limits = gp106_get_internal_sensor_limits, .configure_therm_alert = gp106_configure_therm_alert, }, + .pmu = { + .init_wpr_region = gm20b_pmu_init_acr, + .load_lsfalcon_ucode = gp106_load_falcon_ucode, + .is_lazy_bootstrap = gp106_is_lazy_bootstrap, + .is_priv_load = gp106_is_priv_load, + .prepare_ucode = gp106_prepare_ucode_blob, + .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, + .get_wpr = gp106_wpr_info, + .alloc_blob_space = gp106_alloc_blob_space, + .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, + .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, + .falcon_wait_for_halt = sec2_wait_for_halt, + .falcon_clear_halt_interrupt_status = + sec2_clear_halt_interrupt_status, + .init_falcon_setup_hw = init_sec2_setup_hw1, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .is_pmu_supported = gp106_is_pmu_supported, + .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_is_lpwr_feature_supported = + gp106_pmu_is_lpwr_feature_supported, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_pg_param_post_init = nvgpu_lpwr_post_init, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_pg_init_param = gp106_pg_param_init, + .reset_engine = gp106_pmu_engine_reset, + .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, + }, .clk = { .init_clk_support = gp106_init_clk_support, .get_crystal_clk_hz = gp106_crystal_clk_hz, @@ -532,6 +577,7 @@ int gp106_init_hal(struct gk20a *g) gops->mm = gp106_ops.mm; gops->pramin = gp106_ops.pramin; gops->therm = gp106_ops.therm; + gops->pmu = gp106_ops.pmu; /* * clk must be assigned member by member * since some clk ops are assigned during probe prior to HAL init @@ -568,10 +614,11 @@ int gp106_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); + g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; gp106_init_gr(g); - gp106_init_pmu_ops(g); gp10b_init_uncompressed_kind_map(); gp10b_init_kind_attr(); -- cgit v1.2.2