diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:01:00 -0500 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:35:06 -0500 |
commit | 7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch) | |
tree | 92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/gp106/clk_arb_gp106.c | |
parent | 505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff) | |
parent | 2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff) |
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/clk_arb_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_arb_gp106.c | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c new file mode 100644 index 00000000..b4d1afbc --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c | |||
@@ -0,0 +1,105 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include "gk20a/gk20a.h" | ||
15 | |||
16 | #include "clk/clk_arb.h" | ||
17 | #include "clk_arb_gp106.h" | ||
18 | |||
19 | static u32 gp106_get_arbiter_clk_domains(struct gk20a *g) | ||
20 | { | ||
21 | (void)g; | ||
22 | return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK); | ||
23 | } | ||
24 | |||
25 | static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | ||
26 | u16 *min_mhz, u16 *max_mhz) | ||
27 | { | ||
28 | enum nv_pmu_clk_clkwhich clkwhich; | ||
29 | struct clk_set_info *p0_info; | ||
30 | struct clk_set_info *p5_info; | ||
31 | struct avfsfllobjs *pfllobjs = &(g->clk_pmu.avfs_fllobjs); | ||
32 | |||
33 | u16 limit_min_mhz; | ||
34 | |||
35 | switch (api_domain) { | ||
36 | case CTRL_CLK_DOMAIN_MCLK: | ||
37 | clkwhich = clkwhich_mclk; | ||
38 | break; | ||
39 | |||
40 | case CTRL_CLK_DOMAIN_GPC2CLK: | ||
41 | clkwhich = clkwhich_gpc2clk; | ||
42 | break; | ||
43 | |||
44 | default: | ||
45 | return -EINVAL; | ||
46 | } | ||
47 | |||
48 | p5_info = pstate_get_clk_set_info(g, | ||
49 | CTRL_PERF_PSTATE_P5, clkwhich); | ||
50 | if (!p5_info) | ||
51 | return -EINVAL; | ||
52 | |||
53 | p0_info = pstate_get_clk_set_info(g, | ||
54 | CTRL_PERF_PSTATE_P0, clkwhich); | ||
55 | if (!p0_info) | ||
56 | return -EINVAL; | ||
57 | |||
58 | limit_min_mhz = p5_info->min_mhz; | ||
59 | /* WAR for DVCO min */ | ||
60 | if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK) | ||
61 | if ((pfllobjs->max_min_freq_mhz) && | ||
62 | (pfllobjs->max_min_freq_mhz > limit_min_mhz)) | ||
63 | limit_min_mhz = pfllobjs->max_min_freq_mhz; | ||
64 | |||
65 | *min_mhz = limit_min_mhz; | ||
66 | *max_mhz = p0_info->max_mhz; | ||
67 | |||
68 | return 0; | ||
69 | } | ||
70 | |||
71 | static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, | ||
72 | u16 *default_mhz) | ||
73 | { | ||
74 | enum nv_pmu_clk_clkwhich clkwhich; | ||
75 | struct clk_set_info *p0_info; | ||
76 | |||
77 | switch (api_domain) { | ||
78 | case CTRL_CLK_DOMAIN_MCLK: | ||
79 | clkwhich = clkwhich_mclk; | ||
80 | break; | ||
81 | |||
82 | case CTRL_CLK_DOMAIN_GPC2CLK: | ||
83 | clkwhich = clkwhich_gpc2clk; | ||
84 | break; | ||
85 | |||
86 | default: | ||
87 | return -EINVAL; | ||
88 | } | ||
89 | |||
90 | p0_info = pstate_get_clk_set_info(g, | ||
91 | CTRL_PERF_PSTATE_P0, clkwhich); | ||
92 | if (!p0_info) | ||
93 | return -EINVAL; | ||
94 | |||
95 | *default_mhz = p0_info->max_mhz; | ||
96 | |||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | void gp106_init_clk_arb_ops(struct gpu_ops *gops) | ||
101 | { | ||
102 | gops->clk_arb.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains; | ||
103 | gops->clk_arb.get_arbiter_clk_range = gp106_get_arbiter_clk_range; | ||
104 | gops->clk_arb.get_arbiter_clk_default = gp106_get_arbiter_clk_default; | ||
105 | } | ||