diff options
| author | aalex <aalex@nvidia.com> | 2018-09-07 12:38:05 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-21 06:15:03 -0400 |
| commit | c5810a670d367ae1dc405fcc3108e11265df34bb (patch) | |
| tree | 7ec13fcda49df98f360fb5adc57e4af7a95ea4cc /drivers/gpu/nvgpu/gm20b | |
| parent | ec067c5ed1f00517dbd771fbe9809d2340ec908b (diff) | |
gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl
added hal layer for SM exception mask handling for
taking care of vitualization case.
Jira VQRM-4806
Bug 200447406
Bug 2331747
Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544
Signed-off-by: aalex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1816284
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
| -rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 114d259a..620fbc59 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
| @@ -477,6 +477,7 @@ static const struct gpu_ops gm20b_ops = { | |||
| 477 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 477 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
| 478 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 478 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
| 479 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 479 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
| 480 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
| 480 | }, | 481 | }, |
| 481 | .gr_ctx = { | 482 | .gr_ctx = { |
| 482 | .get_netlist_name = gr_gm20b_get_netlist_name, | 483 | .get_netlist_name = gr_gm20b_get_netlist_name, |