From c5810a670d367ae1dc405fcc3108e11265df34bb Mon Sep 17 00:00:00 2001 From: aalex Date: Fri, 7 Sep 2018 22:08:05 +0530 Subject: gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl added hal layer for SM exception mask handling for taking care of vitualization case. Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544 Signed-off-by: aalex Reviewed-on: https://git-master.nvidia.com/r/1816284 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 114d259a..620fbc59 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -477,6 +477,7 @@ static const struct gpu_ops gm20b_ops = { .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gm20b_get_netlist_name, -- cgit v1.2.2