diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-28 21:36:52 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-02 17:43:25 -0400 |
commit | a15e110a9b790f55a5c6e257cfbf7f7235f5a334 (patch) | |
tree | 199209146e3e67927c13e2ece240de40f973e1ea /drivers/gpu/nvgpu/gm20b | |
parent | 43ae97000be786e4118d431637f05b1462e296c4 (diff) |
gpu: nvgpu: Reorg regops HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
regops sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I7e2ccf158a8e7efa453a3326e86146660f18926f
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530135
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 25 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.c | 65 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.h | 18 |
3 files changed, 54 insertions, 54 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 407a442a..c2bccbee 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -277,6 +277,29 @@ static const struct gpu_ops gm20b_ops = { | |||
277 | .init_therm_setup_hw = gm20b_init_therm_setup_hw, | 277 | .init_therm_setup_hw = gm20b_init_therm_setup_hw, |
278 | .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, | 278 | .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, |
279 | }, | 279 | }, |
280 | .regops = { | ||
281 | .get_global_whitelist_ranges = | ||
282 | gm20b_get_global_whitelist_ranges, | ||
283 | .get_global_whitelist_ranges_count = | ||
284 | gm20b_get_global_whitelist_ranges_count, | ||
285 | .get_context_whitelist_ranges = | ||
286 | gm20b_get_context_whitelist_ranges, | ||
287 | .get_context_whitelist_ranges_count = | ||
288 | gm20b_get_context_whitelist_ranges_count, | ||
289 | .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist, | ||
290 | .get_runcontrol_whitelist_count = | ||
291 | gm20b_get_runcontrol_whitelist_count, | ||
292 | .get_runcontrol_whitelist_ranges = | ||
293 | gm20b_get_runcontrol_whitelist_ranges, | ||
294 | .get_runcontrol_whitelist_ranges_count = | ||
295 | gm20b_get_runcontrol_whitelist_ranges_count, | ||
296 | .get_qctl_whitelist = gm20b_get_qctl_whitelist, | ||
297 | .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, | ||
298 | .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges, | ||
299 | .get_qctl_whitelist_ranges_count = | ||
300 | gm20b_get_qctl_whitelist_ranges_count, | ||
301 | .apply_smpc_war = gm20b_apply_smpc_war, | ||
302 | }, | ||
280 | .mc = { | 303 | .mc = { |
281 | .intr_enable = mc_gk20a_intr_enable, | 304 | .intr_enable = mc_gk20a_intr_enable, |
282 | .intr_unit_config = mc_gk20a_intr_unit_config, | 305 | .intr_unit_config = mc_gk20a_intr_unit_config, |
@@ -350,6 +373,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
350 | gops->fifo = gm20b_ops.fifo; | 373 | gops->fifo = gm20b_ops.fifo; |
351 | gops->gr_ctx = gm20b_ops.gr_ctx; | 374 | gops->gr_ctx = gm20b_ops.gr_ctx; |
352 | gops->therm = gm20b_ops.therm; | 375 | gops->therm = gm20b_ops.therm; |
376 | gops->regops = gm20b_ops.regops; | ||
353 | gops->mc = gm20b_ops.mc; | 377 | gops->mc = gm20b_ops.mc; |
354 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; | 378 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; |
355 | gops->debug = gm20b_ops.debug; | 379 | gops->debug = gm20b_ops.debug; |
@@ -404,7 +428,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
404 | gm20b_init_mm(gops); | 428 | gm20b_init_mm(gops); |
405 | gm20b_init_pmu_ops(g); | 429 | gm20b_init_pmu_ops(g); |
406 | gm20b_init_clk_ops(gops); | 430 | gm20b_init_clk_ops(gops); |
407 | gm20b_init_regops(gops); | ||
408 | 431 | ||
409 | g->name = "gm20b"; | 432 | g->name = "gm20b"; |
410 | 433 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c index 45e7ec3d..1e5f6bfd 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger Driver Register Ops | 2 | * Tegra GK20A GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -377,105 +377,68 @@ static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = { | |||
377 | static const u32 gm20b_qctl_whitelist_ranges_count = | 377 | static const u32 gm20b_qctl_whitelist_ranges_count = |
378 | ARRAY_SIZE(gm20b_qctl_whitelist_ranges); | 378 | ARRAY_SIZE(gm20b_qctl_whitelist_ranges); |
379 | 379 | ||
380 | static const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) | 380 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) |
381 | { | 381 | { |
382 | return gm20b_global_whitelist_ranges; | 382 | return gm20b_global_whitelist_ranges; |
383 | } | 383 | } |
384 | 384 | ||
385 | static int gm20b_get_global_whitelist_ranges_count(void) | 385 | int gm20b_get_global_whitelist_ranges_count(void) |
386 | { | 386 | { |
387 | return gm20b_global_whitelist_ranges_count; | 387 | return gm20b_global_whitelist_ranges_count; |
388 | } | 388 | } |
389 | 389 | ||
390 | static const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void) | 390 | const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void) |
391 | { | 391 | { |
392 | return gm20b_context_whitelist_ranges; | 392 | return gm20b_context_whitelist_ranges; |
393 | } | 393 | } |
394 | 394 | ||
395 | static int gm20b_get_context_whitelist_ranges_count(void) | 395 | int gm20b_get_context_whitelist_ranges_count(void) |
396 | { | 396 | { |
397 | return gm20b_context_whitelist_ranges_count; | 397 | return gm20b_context_whitelist_ranges_count; |
398 | } | 398 | } |
399 | 399 | ||
400 | static const u32 *gm20b_get_runcontrol_whitelist(void) | 400 | const u32 *gm20b_get_runcontrol_whitelist(void) |
401 | { | 401 | { |
402 | return gm20b_runcontrol_whitelist; | 402 | return gm20b_runcontrol_whitelist; |
403 | } | 403 | } |
404 | 404 | ||
405 | static int gm20b_get_runcontrol_whitelist_count(void) | 405 | int gm20b_get_runcontrol_whitelist_count(void) |
406 | { | 406 | { |
407 | return gm20b_runcontrol_whitelist_count; | 407 | return gm20b_runcontrol_whitelist_count; |
408 | } | 408 | } |
409 | 409 | ||
410 | static const | 410 | const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void) |
411 | struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void) | ||
412 | { | 411 | { |
413 | return gm20b_runcontrol_whitelist_ranges; | 412 | return gm20b_runcontrol_whitelist_ranges; |
414 | } | 413 | } |
415 | 414 | ||
416 | static int gm20b_get_runcontrol_whitelist_ranges_count(void) | 415 | int gm20b_get_runcontrol_whitelist_ranges_count(void) |
417 | { | 416 | { |
418 | return gm20b_runcontrol_whitelist_ranges_count; | 417 | return gm20b_runcontrol_whitelist_ranges_count; |
419 | } | 418 | } |
420 | 419 | ||
421 | static const u32 *gm20b_get_qctl_whitelist(void) | 420 | const u32 *gm20b_get_qctl_whitelist(void) |
422 | { | 421 | { |
423 | return gm20b_qctl_whitelist; | 422 | return gm20b_qctl_whitelist; |
424 | } | 423 | } |
425 | 424 | ||
426 | static int gm20b_get_qctl_whitelist_count(void) | 425 | int gm20b_get_qctl_whitelist_count(void) |
427 | { | 426 | { |
428 | return gm20b_qctl_whitelist_count; | 427 | return gm20b_qctl_whitelist_count; |
429 | } | 428 | } |
430 | 429 | ||
431 | static const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void) | 430 | const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void) |
432 | { | 431 | { |
433 | return gm20b_qctl_whitelist_ranges; | 432 | return gm20b_qctl_whitelist_ranges; |
434 | } | 433 | } |
435 | 434 | ||
436 | static int gm20b_get_qctl_whitelist_ranges_count(void) | 435 | int gm20b_get_qctl_whitelist_ranges_count(void) |
437 | { | 436 | { |
438 | return gm20b_qctl_whitelist_ranges_count; | 437 | return gm20b_qctl_whitelist_ranges_count; |
439 | } | 438 | } |
440 | 439 | ||
441 | static int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | 440 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) |
442 | { | 441 | { |
443 | /* Not needed on gm20b */ | 442 | /* Not needed on gm20b */ |
444 | return 0; | 443 | return 0; |
445 | } | 444 | } |
446 | |||
447 | void gm20b_init_regops(struct gpu_ops *gops) | ||
448 | { | ||
449 | gops->regops.get_global_whitelist_ranges = | ||
450 | gm20b_get_global_whitelist_ranges; | ||
451 | gops->regops.get_global_whitelist_ranges_count = | ||
452 | gm20b_get_global_whitelist_ranges_count; | ||
453 | |||
454 | gops->regops.get_context_whitelist_ranges = | ||
455 | gm20b_get_context_whitelist_ranges; | ||
456 | gops->regops.get_context_whitelist_ranges_count = | ||
457 | gm20b_get_context_whitelist_ranges_count; | ||
458 | |||
459 | gops->regops.get_runcontrol_whitelist = | ||
460 | gm20b_get_runcontrol_whitelist; | ||
461 | gops->regops.get_runcontrol_whitelist_count = | ||
462 | gm20b_get_runcontrol_whitelist_count; | ||
463 | |||
464 | gops->regops.get_runcontrol_whitelist_ranges = | ||
465 | gm20b_get_runcontrol_whitelist_ranges; | ||
466 | gops->regops.get_runcontrol_whitelist_ranges_count = | ||
467 | gm20b_get_runcontrol_whitelist_ranges_count; | ||
468 | |||
469 | gops->regops.get_qctl_whitelist = | ||
470 | gm20b_get_qctl_whitelist; | ||
471 | gops->regops.get_qctl_whitelist_count = | ||
472 | gm20b_get_qctl_whitelist_count; | ||
473 | |||
474 | gops->regops.get_qctl_whitelist_ranges = | ||
475 | gm20b_get_qctl_whitelist_ranges; | ||
476 | gops->regops.get_qctl_whitelist_ranges_count = | ||
477 | gm20b_get_qctl_whitelist_ranges_count; | ||
478 | |||
479 | gops->regops.apply_smpc_war = | ||
480 | gm20b_apply_smpc_war; | ||
481 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h index f613668b..4a40184b 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GK20A GPU Debugger Driver Register Ops | 3 | * Tegra GK20A GPU Debugger Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms and conditions of the GNU General Public License, | 8 | * under the terms and conditions of the GNU General Public License, |
@@ -19,6 +19,20 @@ | |||
19 | #ifndef __REGOPS_GM20B_H_ | 19 | #ifndef __REGOPS_GM20B_H_ |
20 | #define __REGOPS_GM20B_H_ | 20 | #define __REGOPS_GM20B_H_ |
21 | 21 | ||
22 | void gm20b_init_regops(struct gpu_ops *gops); | 22 | struct dbg_session_gk20a; |
23 | |||
24 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void); | ||
25 | int gm20b_get_global_whitelist_ranges_count(void); | ||
26 | const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void); | ||
27 | int gm20b_get_context_whitelist_ranges_count(void); | ||
28 | const u32 *gm20b_get_runcontrol_whitelist(void); | ||
29 | int gm20b_get_runcontrol_whitelist_count(void); | ||
30 | const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void); | ||
31 | int gm20b_get_runcontrol_whitelist_ranges_count(void); | ||
32 | const u32 *gm20b_get_qctl_whitelist(void); | ||
33 | int gm20b_get_qctl_whitelist_count(void); | ||
34 | const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void); | ||
35 | int gm20b_get_qctl_whitelist_ranges_count(void); | ||
36 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | ||
23 | 37 | ||
24 | #endif /* __REGOPS_GM20B_H_ */ | 38 | #endif /* __REGOPS_GM20B_H_ */ |