From a15e110a9b790f55a5c6e257cfbf7f7235f5a334 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 28 Jul 2017 18:36:52 -0700 Subject: gpu: nvgpu: Reorg regops HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the regops sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7e2ccf158a8e7efa453a3326e86146660f18926f Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530135 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Tested-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 25 ++++++++++++- drivers/gpu/nvgpu/gm20b/regops_gm20b.c | 65 ++++++++-------------------------- drivers/gpu/nvgpu/gm20b/regops_gm20b.h | 18 ++++++++-- 3 files changed, 54 insertions(+), 54 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 407a442a..c2bccbee 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -277,6 +277,29 @@ static const struct gpu_ops gm20b_ops = { .init_therm_setup_hw = gm20b_init_therm_setup_hw, .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, }, + .regops = { + .get_global_whitelist_ranges = + gm20b_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gm20b_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gm20b_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gm20b_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gm20b_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gm20b_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gm20b_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gm20b_get_qctl_whitelist, + .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gm20b_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gm20b_apply_smpc_war, + }, .mc = { .intr_enable = mc_gk20a_intr_enable, .intr_unit_config = mc_gk20a_intr_unit_config, @@ -350,6 +373,7 @@ int gm20b_init_hal(struct gk20a *g) gops->fifo = gm20b_ops.fifo; gops->gr_ctx = gm20b_ops.gr_ctx; gops->therm = gm20b_ops.therm; + gops->regops = gm20b_ops.regops; gops->mc = gm20b_ops.mc; gops->dbg_session_ops = gm20b_ops.dbg_session_ops; gops->debug = gm20b_ops.debug; @@ -404,7 +428,6 @@ int gm20b_init_hal(struct gk20a *g) gm20b_init_mm(gops); gm20b_init_pmu_ops(g); gm20b_init_clk_ops(gops); - gm20b_init_regops(gops); g->name = "gm20b"; diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c index 45e7ec3d..1e5f6bfd 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c @@ -1,7 +1,7 @@ /* * Tegra GK20A GPU Debugger Driver Register Ops * - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -377,105 +377,68 @@ static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = { static const u32 gm20b_qctl_whitelist_ranges_count = ARRAY_SIZE(gm20b_qctl_whitelist_ranges); -static const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) +const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) { return gm20b_global_whitelist_ranges; } -static int gm20b_get_global_whitelist_ranges_count(void) +int gm20b_get_global_whitelist_ranges_count(void) { return gm20b_global_whitelist_ranges_count; } -static const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void) +const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void) { return gm20b_context_whitelist_ranges; } -static int gm20b_get_context_whitelist_ranges_count(void) +int gm20b_get_context_whitelist_ranges_count(void) { return gm20b_context_whitelist_ranges_count; } -static const u32 *gm20b_get_runcontrol_whitelist(void) +const u32 *gm20b_get_runcontrol_whitelist(void) { return gm20b_runcontrol_whitelist; } -static int gm20b_get_runcontrol_whitelist_count(void) +int gm20b_get_runcontrol_whitelist_count(void) { return gm20b_runcontrol_whitelist_count; } -static const -struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void) +const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void) { return gm20b_runcontrol_whitelist_ranges; } -static int gm20b_get_runcontrol_whitelist_ranges_count(void) +int gm20b_get_runcontrol_whitelist_ranges_count(void) { return gm20b_runcontrol_whitelist_ranges_count; } -static const u32 *gm20b_get_qctl_whitelist(void) +const u32 *gm20b_get_qctl_whitelist(void) { return gm20b_qctl_whitelist; } -static int gm20b_get_qctl_whitelist_count(void) +int gm20b_get_qctl_whitelist_count(void) { return gm20b_qctl_whitelist_count; } -static const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void) +const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void) { return gm20b_qctl_whitelist_ranges; } -static int gm20b_get_qctl_whitelist_ranges_count(void) +int gm20b_get_qctl_whitelist_ranges_count(void) { return gm20b_qctl_whitelist_ranges_count; } -static int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) +int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) { /* Not needed on gm20b */ return 0; } - -void gm20b_init_regops(struct gpu_ops *gops) -{ - gops->regops.get_global_whitelist_ranges = - gm20b_get_global_whitelist_ranges; - gops->regops.get_global_whitelist_ranges_count = - gm20b_get_global_whitelist_ranges_count; - - gops->regops.get_context_whitelist_ranges = - gm20b_get_context_whitelist_ranges; - gops->regops.get_context_whitelist_ranges_count = - gm20b_get_context_whitelist_ranges_count; - - gops->regops.get_runcontrol_whitelist = - gm20b_get_runcontrol_whitelist; - gops->regops.get_runcontrol_whitelist_count = - gm20b_get_runcontrol_whitelist_count; - - gops->regops.get_runcontrol_whitelist_ranges = - gm20b_get_runcontrol_whitelist_ranges; - gops->regops.get_runcontrol_whitelist_ranges_count = - gm20b_get_runcontrol_whitelist_ranges_count; - - gops->regops.get_qctl_whitelist = - gm20b_get_qctl_whitelist; - gops->regops.get_qctl_whitelist_count = - gm20b_get_qctl_whitelist_count; - - gops->regops.get_qctl_whitelist_ranges = - gm20b_get_qctl_whitelist_ranges; - gops->regops.get_qctl_whitelist_ranges_count = - gm20b_get_qctl_whitelist_ranges_count; - - gops->regops.apply_smpc_war = - gm20b_apply_smpc_war; -} diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h index f613668b..4a40184b 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h @@ -2,7 +2,7 @@ * * Tegra GK20A GPU Debugger Driver Register Ops * - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,6 +19,20 @@ #ifndef __REGOPS_GM20B_H_ #define __REGOPS_GM20B_H_ -void gm20b_init_regops(struct gpu_ops *gops); +struct dbg_session_gk20a; + +const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void); +int gm20b_get_global_whitelist_ranges_count(void); +const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void); +int gm20b_get_context_whitelist_ranges_count(void); +const u32 *gm20b_get_runcontrol_whitelist(void); +int gm20b_get_runcontrol_whitelist_count(void); +const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void); +int gm20b_get_runcontrol_whitelist_ranges_count(void); +const u32 *gm20b_get_qctl_whitelist(void); +int gm20b_get_qctl_whitelist_count(void); +const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void); +int gm20b_get_qctl_whitelist_ranges_count(void); +int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); #endif /* __REGOPS_GM20B_H_ */ -- cgit v1.2.2