gpu: nvgpu: gm20b: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I1651ae8ee680bdeb48606569c4e8c2fc7cb87f20
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805077
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index acdf4591..27daccb6 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -716,8 +716,9 @@ int gm20b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
         /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
-        if (gops->fuse.check_priv_security(g))
+        if (gops->fuse.check_priv_security(g)) {
                 return -EINVAL; /* Do not boot gpu */
+        }
 
         /* priv security dependent ops */
         if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {