gpu: nvgpu: add fault_ch to record_sm_error_state

fault_ch is needed by rm-server to send the notification to guest VM.
rm-server is going to use gr sources from linux

Jira VQRM-2982

Change-Id: Ifb6e8a9630a471d07b89ffaa7f2ceb309220fd21
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1661665
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index bddf6412..3f604028 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -116,7 +116,8 @@ void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem);
 void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
 void gr_gm20b_get_access_map(struct gk20a *g,
                                    u32 **whitelist, int *num_entries);
-int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc);
+int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc,
+                u32 tpc, struct channel_gk20a *fault_ch);
 int gm20b_gr_update_sm_error_state(struct gk20a *g,
                 struct channel_gk20a *ch, u32 sm_id,
                 struct nvgpu_gr_sm_error_state *sm_error_state);