gpu: nvgpu: remove clk writel from TPC FS

To floorsweep any TPC on gm20b, we first have to
set BIT(28) in CLK_RST_CONTROLLER_MISC_CLK_ENB_0
from nvgpu driver

But now this bit is set by default from clock
driver, hence remove clk_writel() from nvgpu
driver

Bug 200262155

Change-Id: I65bc60cb017109bdb882d83637f2a06d27586f18
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1265752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 0 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index fd24d105..84eb3862 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -28,12 +28,6 @@ enum {
         MAXWELL_CHANNEL_GPFIFO_A= 0xB06F,
 };
 
-#define tegra_clk_writel(value, offset) \
-        writel(value, IO_ADDRESS(0x60006000 + offset))
-
-#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0               0x48
-#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE   BIT(28)
-
 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
 #define FUSE_FUSEBYPASS_0                               0x24
 #define FUSE_WRITE_ACCESS_SW_0                          0x30