From 145225b896bd43a918280de27260ba5a315751c8 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 6 Dec 2016 15:03:08 +0530 Subject: gpu: nvgpu: remove clk writel from TPC FS To floorsweep any TPC on gm20b, we first have to set BIT(28) in CLK_RST_CONTROLLER_MISC_CLK_ENB_0 from nvgpu driver But now this bit is set by default from clock driver, hence remove clk_writel() from nvgpu driver Bug 200262155 Change-Id: I65bc60cb017109bdb882d83637f2a06d27586f18 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1265752 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index fd24d105..84eb3862 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -28,12 +28,6 @@ enum { MAXWELL_CHANNEL_GPFIFO_A= 0xB06F, }; -#define tegra_clk_writel(value, offset) \ - writel(value, IO_ADDRESS(0x60006000 + offset)) - -#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0 0x48 -#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE BIT(28) - #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) #define FUSE_FUSEBYPASS_0 0x24 #define FUSE_WRITE_ACCESS_SW_0 0x30 -- cgit v1.2.2