gpu: nvgpu: Move programming FB phys access to FB

FB physical access register for simulation was programmed in GR
implementation. Move it to FB where it belongs.

JIRA NVGPU-714

Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772915
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index f9eb97ce..85da0d35 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -49,11 +49,6 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
 
         nvgpu_log_info(g, "initialize gpc mmu");
 
-        if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
-                /* Bypass MMU check for non-secure boot. For
-                 * secure-boot,this register write has no-effect */
-                gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
-        }
         temp = gk20a_readl(g, fb_mmu_ctrl_r());
         temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
                 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |