From da03aa782535e77e221a3c27b0676fe9c1c7980c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 6 Jul 2018 10:03:31 -0700 Subject: gpu: nvgpu: Move programming FB phys access to FB FB physical access register for simulation was programmed in GR implementation. Move it to FB where it belongs. JIRA NVGPU-714 Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1772915 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index f9eb97ce..85da0d35 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -49,11 +49,6 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g) nvgpu_log_info(g, "initialize gpc mmu"); - if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { - /* Bypass MMU check for non-secure boot. For - * secure-boot,this register write has no-effect */ - gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); - } temp = gk20a_readl(g, fb_mmu_ctrl_r()); temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | -- cgit v1.2.2