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authorseshendra Gadagottu <sgadagottu@nvidia.com>2016-07-27 20:06:36 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-10-11 12:16:03 -0400
commitfda4ddfa79f3a78becfe44fd558974bd274c03a9 (patch)
tree55d7999d7af7040ed50121fa6fa70fddc11b0887 /drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
parentbb5fd16c67287e53db5165a974ea15ec3be09fe9 (diff)
gpu: nvgpu: userd allocation from sysmem
When bar1 memory is not supported then userd will be allocated from sysmem. Functions gp_get and gp_put are updated accordingly. JIRA GV11B-1 Change-Id: Ia895712a110f6cca26474228141488f5f8ace756 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1225384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index b5b9c52b..07ad322a 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -15,6 +15,7 @@
15 15
16#include <linux/delay.h> 16#include <linux/delay.h>
17#include "gk20a/gk20a.h" 17#include "gk20a/gk20a.h"
18#include "gk20a/fifo_gk20a.h"
18#include "fifo_gm20b.h" 19#include "fifo_gm20b.h"
19#include "hw_ccsr_gm20b.h" 20#include "hw_ccsr_gm20b.h"
20#include "hw_ram_gm20b.h" 21#include "hw_ram_gm20b.h"
@@ -133,6 +134,7 @@ static void gm20b_device_info_data_parse(struct gk20a *g,
133} 134}
134void gm20b_init_fifo(struct gpu_ops *gops) 135void gm20b_init_fifo(struct gpu_ops *gops)
135{ 136{
137 gops->fifo.init_fifo_setup_hw = gk20a_init_fifo_setup_hw;
136 gops->fifo.bind_channel = channel_gm20b_bind; 138 gops->fifo.bind_channel = channel_gm20b_bind;
137 gops->fifo.unbind_channel = channel_gk20a_unbind; 139 gops->fifo.unbind_channel = channel_gk20a_unbind;
138 gops->fifo.disable_channel = channel_gk20a_disable; 140 gops->fifo.disable_channel = channel_gk20a_disable;
@@ -142,6 +144,8 @@ void gm20b_init_fifo(struct gpu_ops *gops)
142 gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; 144 gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc;
143 gops->fifo.channel_set_priority = gk20a_channel_set_priority; 145 gops->fifo.channel_set_priority = gk20a_channel_set_priority;
144 gops->fifo.channel_set_timeslice = gk20a_channel_set_timeslice; 146 gops->fifo.channel_set_timeslice = gk20a_channel_set_timeslice;
147 gops->fifo.userd_gp_get = gk20a_userd_gp_get;
148 gops->fifo.userd_gp_put = gk20a_userd_gp_put;
145 149
146 gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; 150 gops->fifo.preempt_channel = gk20a_fifo_preempt_channel;
147 gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; 151 gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg;