gpu: nvgpu: add and reorg reset_enable_hw fifo ops

fifo reset_enable_hw is reorged to clear and enable pbdma/fifo interrupts
after all the required configuration such as configuring timeouts,
enabling timeout detections are taken care of.

JIRA GPUT19X-74
JIRA GPUT19X-47

Change-Id: Id780cc11d858db18f8d748c037954ede73298506
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325351
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 5a0bd39e..f09da825 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -223,4 +223,5 @@ void gm20b_init_fifo(struct gpu_ops *gops)
         gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask;
         gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending;
         gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs;
+        gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw;
 }